Datasheet

TPS65023, TPS65023B
www.ti.com SLVS670J –JUNE 2006– REVISED SEPTEMBER 2011
Table 4. I
2
C Timing
I2C timing for TPS65023 MIN MAX UNIT
f
MAX
Clock frequency 400 kHz
t
wH(HIGH)
Clock high time 600 ns
t
wL(LOW)
Clock low time 1300 ns
t
R
DATA and CLK rise time 300 ns
t
F
DATA and CLK fall time 300 ns
t
h(STA)
Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns
t
su(DATA)
Setup time for repeated START condition 600 ns
t
h(DATA)
Data input hold time 300 ns
t
su(DATA)
Data input setup time 300 ns
t
su(STO)
STOP condition setup time 600 ns
t
(BUF)
Bus free time 1300 ns
I2C timing for TPS65023B MIN MAX UNIT
Operating conditions:
VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 2.5V to 5.5V,
VBACKUP = 3.0V,
T
A
= -40 °C to +85 °C
f
MAX
Clock frequency 400 kHz
t
wH(HIGH)
Clock high time 600 ns
t
wL(LOW)
Clock low time 1300 ns
t
R
DATA and CLK rise time 300 ns
t
F
DATA and CLK fall time 300 ns
t
h(STA)
Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns
t
su(DATA)
Setup time for repeated START condition 600 ns
t
h(DATA)
Data input hold time 100 ns
t
su(DATA)
Data input setup time 100 ns
t
su(STO)
STOP condition setup time 600 ns
t
(BUF)
Bus free time 1300 ns
VERSION. Register Address: 00h (read only)
VERSION B7 B6 B5 B4 B3 B2 B1 B0
Bit name and 0 0 1 0 0 0 1 1
function
Read/Write R R R R R R R R
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