Datasheet

DataLine
Stable;
DataValid
DATA
CLK
Change
ofData
Allowed
DATA
CLK
CE
S
P
STARTCondition STOP Condition
SCLK
SDAT
Start Slave Address
Register Address
Data
0
A6
A5
A4
A0
R/W
R7
R6
R5
R0
D7
D6
D5
D0
ACK ACK ACK
0 0
0
Stop
Note: SLAVE = TPS65023
TPS65023, TPS65023B
www.ti.com SLVS670J –JUNE 2006– REVISED SEPTEMBER 2011
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start
condition and terminated with a stop condition. When addressed, the TPS65023, TPS65023B device generates
an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra
clock pulse that is associated with the acknowledge bit. The TPS65023, TPS65023B device must pull down the
DATA line during the acknowledge clock pulse so that the DATA line is a stable low during the high period of the
acknowledge clock pulse. The DATA line is a stable low during the high period of the acknowledge–related clock
pulse. Setup and hold times must be taken into account. During read operations, a master must signal the end of
data to the slave by not generating an acknowledge bit on the last byte that was clocked out of the slave. In this
case, the slave TPS65023, TPS65023B device must leave the data line high to enable the master to generate
the stop condition
Figure 30. Bit Transfer on the Serial Interface
Figure 31. START and STOP Conditions
Figure 32. Serial i/f WRITE to TPS65023, TPS65023B Device
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Product Folder Link(s) :TPS65023 TPS65023B