Datasheet

Vin
min
+ Vout
min
) Iout
max
ǒ
r
DS(on)
max ) R
L
Ǔ
TPS65023, TPS65023B
SLVS670J –JUNE 2006– REVISED SEPTEMBER 2011 www.ti.com
These control methods reduce the quiescent current to typically 14 μA per converter, and the switching activity to
a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal
output voltage at light load current results in a low output voltage ripple. The ripple depends on the comparator
delay and the size of the output capacitor. Increasing capacitor values makes the output ripple tend to zero. The
PSM is disabled through the I
2
C interface to force the individual converters to stay in fixed frequency PWM
mode.
LOW RIPPLE MODE
Setting Bit 3 in register CON-CTRL to 1 enables the low ripple mode for all of the dc-dc converters if operated in
PFM mode. For an output current less than approximately 10 mA, the output voltage ripple in PFM mode is
reduced, depending on the actual load current. The lower the actual output current on the converter, the lower
the output ripple voltage. For an output current above 10 mA, there is only minor difference in output voltage
ripple between PFM mode and low ripple PFM mode. As this feature also increases switching frequency, it is
used to keep the switching frequency above the audible range in PFM mode down to a low output current.
SOFT START
Each of the three converters has an internal soft start circuit that limits the inrush current during start-up. The soft
start is realized by using a low current to initially charge the internal compensation capacitor. The soft start time
is typically 750 μs if the output voltage ramps from 5% to 95% of the final target value. If the output is already
precharged to some voltage when the converter is enabled, then this time is reduced proportionally. There is a
short delay of typically 170 μs between the converter being enabled and switching activity actually starting. This
allows the converter to bias itself properly, to recognize if the output is precharged, and if so to prevent
discharging of the output while the internal soft start ramp catches up with the output voltage.
100% DUTY CYCLE LOW DROPOUT OPERATION
The TPS65023, TPS65023B converters offer a low input to output voltage difference while still maintaining
operation with the use of the 100% duty cycle mode. In this mode the P-channel switch is constantly turned on.
This is particularly useful in battery-powered applications to achieve longest operation time by taking full
advantage of the whole battery voltage range. The minimum input voltage required to maintain dc regulation
depends on the load current and output voltage. It is calculated as:
(3)
with:
Iout
max
= maximum load current (Note: ripple current in the inductor is zero under these conditions)
r
DS(on)
max = maximum P-channel switch r
DS(on)
R
L
= DC resistance of the inductor
Vout
min
= nominal output voltage minus 2% tolerance limit
ACTIVE DISCHARGE WHEN DISABLED
When the VDCDC1, VDCDC2, and VDCDC3 converters are disabled, due to an UVLO, DCDC_EN or
OVERTEMP condition, it is possible to actively pull down the outputs. This feature is disabled per default and is
individually enabled via the CON_CTRL2 register in the serial interface. When this feature is enabled, the
VDCDC1, VDCDC2, and VDCDC3 outputs are discharged by a 300 Ω (typical) load which is active as long as
the converters are disabled.
POWER GOOD MONITORING
All three step-down converters and both the LDO1 and LDO2 linear regulators have power good comparators.
Each comparator indicates when the relevant output voltage has dropped 10% below its target value with 5%
hysteresis. The outputs of these comparators are available in the PGOODZ register via the serial interface. An
interrupt is generated when any voltage rail drops below the 10% threshold. The comparators are disabled when
the converters are disabled and the relevant PGOODZ register bits indicate that power is good.
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