Datasheet

TPS65023, TPS65023B
SLVS670J –JUNE 2006– REVISED SEPTEMBER 2011 www.ti.com
PIN FUNCTIONS (continued)
PIN
I/O DESCRIPTION
NAME NO.
Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters.
VCC 37 I VCC must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2.
VCC also supplies serial interface block.
Input signal indicating default VDCDC1 voltage, 0 = 1.2 V, 1 = 1.6 V DEFDCDC1 can also be
DEFDCDC1 10 I connected to a resistor divider between VDCDC1 and GND, if the output voltage of the DCDC1
converter is set in a range from 0.6 V to VINDCDC1 V.
Input signal indicating default VDCDC2 voltage, 0 = 1.8 V, 1 = 3.3 V DEFDCDC2 can also be
DEFDCDC2 32 I connected to a resistor divider between VDCDC2 and GND, if the output voltage of the DCDC2
converter is set in a range from 0.6 V to VINDCDC2 V.
Input signal indicating default VDCDC3 voltage, 0 = 1.8 V, 1 = 3.3 V DEFDCDC3 can also be
DEFDCDC3 1 I connected to a resistor divider between VDCDC3 and GND, if the output voltage of the DCDC3
converter is set in a range from 0.6 V to VINDCDC3 V.
DCDC1_EN 25 I VDCDC1 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC2_EN 24 I VDCDC2 enable pin. A logic high enables the regulator, a logic low disables the regulator.
DCDC3_EN 23 I VDCDC3 enable pin. A logic high enables the regulator, a logic low disables the regulator.
LDO REGULATOR SECTION
VINLDO 19 I Input voltage for LDO1 and LDO2
VLDO1 20 O Output voltage of LDO1
VLDO2 18 O Output voltage of LDO2
LDO_EN 22 I Enable input for LDO1 and LDO2. A Logic high enables the LDOs, a logic low disables the LDOs.
VBACKUP 15 I Connect the backup battery to this input pin.
VRTC 16 O Output voltage of the LDO/switch for the real time clock.
VSYSIN 14 I Input of system voltage for VRTC switch.
DEFLD01 12 I Digital input. DEFLD01 sets the default output voltage of LDO1 and LDO2.
DEFLD02 13 I Digital input. DEFLD02 sets the default output voltage of LDO1 and LDO2.
CONTROL AND I
2
C SECTION
HOT_RESET 11 I Push button input that reboots or wakes up the processor via RESPWRON output pin.
TRESPWRON 26 I Connect the timing capacitor to TRESPWRON to set the reset delay time: 1 nF → 100 ms.
RESPWRON 27 O Open drain system reset output.
PWRFAIL 31 O Open drain output. Active low when PWRFAIL comparator indicates low VBAT condition.
LOW_BAT 21 O Open drain output of LOW_BAT comparator.
INT 28 O Open drain output
SCLK 30 I Serial interface clock line
SDAT 29 I/O Serial interface data/address
PWRFAIL_SNS 38 I Input for the comparator driving the PWRFAIL output.
LOWBAT_SNS 39 I Input for the comparator driving the LOW_BAT output.
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