Datasheet

TPS65022
SLVS667A –JULY 2006– REVISED SEPTEMBER 2011 www.ti.com
DEFCORE. Register Address: 06h (read/write Default Value: 14h/1Eh
DEFCORE B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function CORE4 CORE3 CORE2 CORE1 CORE0
Default 0 0 0 1 DEFDCDC3 1 DEFDCDC3 0
Default value loaded by: RESET(2) RESET(1) RESET(1) RESET(1) RESET(2)
Read/Write R/W R/W R/W R/W R/W
RESET(1): DEFCORE[3:1] are reset to the default RESET(2): DEFCORE[4] and DEFCORE[0] are reset
value by one of these events: to the default value by one of these events:
• undervoltage lockout (UVLO) • undervoltage lockout (UVLO)
• DCDC1_EN and DCDC3_EN pulled low • DCDC1_EN pulled low
• HOT_RESET pulled low • HOT_RESET pulled low
• RESPWRON active • RESPWRON active
• VRTC below threshold • VRTC below threshold
CORE4 CORE3 CORE2 CORE1 CORE0 VDCDC3 CORE4 CORE3 CORE2 CORE1 CORE0 VDCDC3
0 0 0 0 0 0.8 V 1 0 0 0 0 1.2 V
0 0 0 0 1 0.825 V 1 0 0 0 1 1.225 V
0 0 0 1 0 0.85 V 1 0 0 1 0 1.25 V
0 0 0 1 1 0.875 V 1 0 0 1 1 1.275 V
0 0 1 0 0 0.9 V 1 0 1 0 0 1.3 V
0 0 1 0 1 0.925 V 1 0 1 0 1 1.325 V
0 0 1 1 0 0.95 V 1 0 1 1 0 1.35 V
0 0 1 1 1 0.975 V 1 0 1 1 1 1.375 V
0 1 0 0 0 1 V 1 1 0 0 0 1.4 V
0 1 0 0 1 1.025 V 1 1 0 0 1 1.425 V
0 1 0 1 0 1.05 V 1 1 0 1 0 1.45 V
0 1 0 1 1 1.075 V 1 1 0 1 1 1.475 V
0 1 1 0 0 1.1 V 1 1 1 0 0 1.5 V
0 1 1 0 1 1.125 V 1 1 1 0 1 1.525 V
0 1 1 1 0 1.15 V 1 1 1 1 0 1.55 V
0 1 1 1 1 1.175 V 1 1 1 1 1 1.6 V
DEFSLEW. Register Address: 07h (read/write) Default Value: 06h
DEFSLEW B7 B6 B5 B4 B3 B2 B1 B0
Bit name and function SLEW2 SLEW1 SLEW0
Default 1 1 0
Default value loaded by: UVLO UVLO UVLO
Read/Write R/W R/W R/W
SLEW2 SLEW1 SLEW0 VDCDC3 SLEW RATE
0 0 0 0.15 mV/μs
0 0 1 0.3 mV/μs
0 1 0 0.6 mV/μs
0 1 1 1.2 mV/μs
1 0 0 2.4 mV/μs
1 0 1 4.8 mV/μs
1 1 0 9.6 mV/μs
1 1 1 Immediate
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