Datasheet

V
CC
DCDC1_EN
t
NRESPWRON
V DCDC1
O
V DCDC2
O
V DCDC3
O
RESPWRON
RampWithin800 sm
RampWithin
800 sm
RampWithin
800 sm
RampWithin800 sm
RampWithin800 sm
DEFCORE
register
SlopeDepending
OnLoad
GObitin
CON_CTRL2
2.5Vor1.8V
DCDC2_EN
3.3Vor3V
DCDC3_EN
1.3Vor1.55V
DefaultValue
SetHigherOutputVoltageforDCDC3
Programmed
SlewRate
Cleared Automatically
1.3Vor1.55V
AutomaticallySet
toDefaultValue
TPS65022
SLVS667A –JULY 2006– REVISED SEPTEMBER 2011 www.ti.com
Figure 28. DVS Timing
SERIAL INTERFACE
The serial interface is compatible with the standard and fast mode I
2
C specifications, allowing transfers at up to
400 kHz. The interface adds flexibility to the power supply solution, enabling most functions to be programmed to
new values depending on the instantaneous application requirements and charger status to be monitored.
Register contents remain intact as long as VCC remains above 2 V. The TPS65022 has a 7-bit address:
1001000, other addresses are available upon contact with the factory. Attempting to read data from the register
addresses not listed in this section results in FFh being read out.
For normal data transfer, DATA is allowed to change only when CLK is low. Changes when CLK is high are
reserved for indicating the start and stop conditions. During data transfer, the data line must remain stable
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