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TPS65022

www.ti.com

SLVS667A –JULY 2006– REVISED SEPTEMBER 2011

POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS

Check for Samples: TPS65022

FEATURES

DESCRIPTION

The TPS65022 is an integrated Power Management

234

• 1.2 A, 97% Efficient Step-Down Converter for

IC for applications powered by one Li-Ion or

System Voltage (VDCDC1)

Li-Polymer cell, and which require multiple power

• 1 A, Up to 95% Efficient Step-Down Converter

rails. The TPS65022 provides three highly efficient,

for Memory Voltage (VDCDC2)

step-down converters targeted at providing the core

voltage, peripheral, I/O and memory rails in a

• 900 mA, 90% Efficient Step-Down Converter

processor based system. All three step-down

for Processor Core (VDCDC3)

converters enter a low-power mode at light load for

• 30 mA LDO/Switch for Real Time Clock (VRTC)

maximum efficiency across the widest possible range

• 2 x 200 mA General-Purpose LDO

of load currents. The TPS65022 also integrates two

general-purpose 200 mA LDO voltage regulators,

• Dynamic Voltage Management for Processor

which are enabled with an external input pin. Each

Core

LDO operates with an input voltage range between

• Preselectable LDO Voltage Using Two Digital

1.5 V and 6.5 V, allowing them to be supplied from

Input Pins

one of the step-down converters or directly from the

• Externally Adjustable Reset Delay Time

battery. The default output voltage of the LDOs can

be digitally set to 4 different voltage combinations

• Battery Backup Functionality

using the DEFLDO1 and DEFLDO2 pins. The serial

• Separate Enable Pins for Inductive Converters

interface can be used for dynamic voltage scaling,

• I

C™ Compatible Serial Interface

masking interrupts, or for dis/enabling and setting the

LDO output voltages. The interface is compatible with

• 85-μA Quiescent Current

the Fast/Standard mode I

C specification, allowing

• Low Ripple PFM Mode

transfers at up to 400 kHz. The TPS65022 is

• Thermal Shutdown Protection

available in a 40-pin (RHA) QFN package, and

operates over a free-air temperature of -40°C to

• 40-Pin 6 mm x 6 mm QFN Package

85°C.

APPLICATIONS

• PDA

• Cellular/Smart Phone

• Internet Audio Player

• Digital Still Camera

• Digital Radio Player

• Split Supply TMS320™ DSP Family and μP

Solutions:

OMAP™1610, OMAP1710, OMAP330, XScale

Bulverde, Samsung ARM-Based Processors,

etc.

• Intel

PXA270, etc.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2TMS320, OMAP, PowerPAD are trademarks of Texas Instruments.

3Intel is a registered trademark of Intel Corporation.

C is a trademark of NXP B.V. Corporation.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (49 pages)

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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com POWER MANAGEMENT IC FOR LI-ION POWERED SYSTEMS Check for Samples: TPS65022 FEATURES DESCRIPTION • 1.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS over operating free-air temperature range (unless otherwise noted) MIN VCC VO NOM MAX Input voltage range step-down convertors (VINDCDC1, VINDCDC2, VINDCDC3); pins need to be tied to the same voltage rail 2.5 6 Output voltage range for VDCDC1 step-down convertor (1) 0.6 VINDCDC1 Output voltage range for VDCDC2 (mem) step-down convertor (1) 0.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT CONTROL SIGNALS : SCLK, SDAT (input), DCDC1_EN, DCDC2_EN, DCDC3_EN, LDO_EN, DEFLDO1, DEFLDO2 VIH High level input voltage Rpullup at SCLK and SDAT = 4.7 kΩ, pulled to VRTC 1.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT SUPPLY PINS: VCC, VINDCDC1, VINDCDC2, VINDCDC3 I(q) II I(q) Operating quiescent current, PFM Current into VCC; PWM Quiescent current All 3 DCDC converters enabled, zero load and no switching, LDOs enabled VCC = 3.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 20 33 μA 3 μA SUPPLY PINS: VBACKUP, VSYSIN, VRTC I(q) Operating quiescent current VBACKUP = 3 V, VSYSIN = 0 V; VCC = 2.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC1 STEP-DOWN CONVERTER VI Input voltage range, VINDCDC1 IO Maximum output current I(SD) Shutdown supply current in VINDCDC1 DCDC1_EN = GND 0.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC2 STEP-DOWN CONVERTER VI Input voltage range, VINDCDC2 IO Maximum output current 2.5 I(SD) Shutdown supply current in VINDCDC2 DCDC2_EN = GND 0.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VDCDC3 STEP-DOWN CONVERTER VI Input voltage range, VINDCDC3 2.5 IO Maximum output current 900 I(SD) Shutdown supply current in VINDCDC3 DCDC3_EN = GND 0.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS VINDCDC1 = VINDCDC2 = VINDCDC3 = VCC = VINLDO = 3.6 V, VBACKUP = 3 V, TA = –40°C to 85°C, typical values are at TA = 25°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT VLDO1 and VLDO2 LOW DROPOUT REGULATORS VI Input voltage range for LDO1, 2 1.5 6.5 V VO LDO1 output voltage range 1 3.3 V VO LDO2 output voltage range 1 3.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com PIN FUNCTIONS (continued) PIN NAME NO. I/O DESCRIPTION VCC 37 I Power supply for digital and analog circuitry of VDCDC1, VDCDC2, and VDCDC3 dc-dc converters. This must be connected to the same voltage supply as VINDCDC3, VINDCDC1, and VINDCDC2. Also supplies serial interface block DEFDCDC1 10 I Input signal indicating default VDCDC1 voltage, 0 = 3 V, 1 = 3.3 V.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS Graphs were taken using the EVM with the following inductor/output capacitor combinations: CONVERTER INDUCTOR OUTPUT CAPACITOR OUTPUT CAPACITOR VALUE VDCDC1 VLCF4020-2R2 C2012X5R0J106M 2 × 10 μF VDCDC2 VLCF4020-2R2 C2012X5R0J106M 2 × 10 μF VDCDC3 VLF4012AT-2R2M1R5 C2012X5R0J106M 2 × 10 μF Table 1.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com DCDC2: EFFICIENCY vs OUTPUT CURRENT DCDC2: EFFICIENCY vs OUTPUT CURRENT VI = 2.5 V VI = 3.8 V Efficiency - % Efficiency - % VI = 3.8 V VI = 4.2 V VI = 4.2 V VI = 2.5 V VI = 5 V VI = 5 V o o TA = 25 C VO = 1.8 V PWM Mode TA = 25 C VO = 1.8 V PWM / PFM Mode 0.01 0.1 10 1 100 1k 10 k 0.01 0.1 10 1 IO - Output Current - mA 100 1k 10 k IO - Output Current - mA Figure 3. Figure 4.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com DCDC3: EFFICIENCY vs OUTPUT CURRENT VDCDC1 LINE TRANSIENT RESPONSE Ch1 = VI Ch2 = VO Efficiency - % VI = 3 V C1 High 4.74 V VI = 3.8 V VI = 2.5 V C1 Low 3.08 V VI = 4.2 V C2 PK-PK 85 mV VI = 5 V C2 Mean 3.2957 V IO = 100 mA VI = 3.6 V to 4.7 V VO = 3 V PWM Mode o TA = 25 C VO = 1.3 V Low Ripple PFM Mode 0.01 0.1 10 1 IO - Output Current - mA Figure 7. Figure 8.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com VDCDC1 LOAD TRANSIENT RESPONSE VDCDC2 LOAD TRANSIENT RESPONSE Ch2 = VO Ch4 = IO Ch2 = VO Ch4 = IO C4 High 1.09 A C4 High 830 mA C4 Low 120 mA C4 Low 90 mA C2 PK-PK 188 mV C2 PK-PK 80 mV C2 Mean 3.3051 V C2 Mean 1.7946 V IO = 100 mA to 800 mA VI = 3.8 V IO = 120 mA to 1080 mA VI = 3.8 V VO = 1.8 V PWM Mode VO = 3.3 V PWM Mode Figure 11. Figure 12.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com VDCDC2 OUTPUT VOLTAGE RIPPLE VO = 1.8 V VI = 3.8 V IO = 1 mA o TA = 25 C Low Ripple PFM Mode VDCDC2 OUTPUT VOLTAGE RIPPLE VI = 3.8 V VO = 1.8 V IO = 1 mA TA = 25oC PWM Mode C2 PK-PK 7.7 mV C2 Mean 1.79955 mV Figure 15. Figure 16. STARTUP VDCDC1, VDCDC2, AND VDCDC3 STARTUP LDO1 AND LDO2 ENABLE ENABLE VDCDC1 LDO1 VDCDC2 LDO2 VDCDC3 Figure 17. 18 Figure 18.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com LDO1 LINE TRANSIENT RESPONSE Ch1 = VI Ch2 = VO IO = 25 mA VO = 1.1 V o TA = 25 C LDO2 LINE TRANSIENT RESPONSE C1 High 3.83 V Ch1 = VI Ch2 = VO IO = 25 mA VO = 3.3 V TA = 25oC C1 Low 3.29 V C1 Low 3.99 V C2 PK-PK 6.2 mV C2 PK-PK 6.1 mV C2 Mean 1.09702 V Ch1 = VI Ch2 = VO C2 Mean 3.29828 V Figure 19. Figure 20. VRTC LINE TRANSIENT RESPONSE LDO1 LOAD TRANSIENT RESPONSE IO = 10 mA VO = 3 V o TA = 25 C C1 High 4.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com LDO2 LOAD TRANSIENT RESPONSE VRTC LOAD TRANSIENT RESPONSE C4 High 47.8 mA C4 High 21.4 mA C4 Low -2.9 mA C4 Low -1.4 mA C2 PK-PK 40.4 mV C2 PK-PK 76 mV C2 Mean 3.29821 V VI = 4 V VO = 3.3 V o TA = 25 C Ch2 = VO Ch4 = IO C2 Mean 2.9762 V Ch2 = VO Ch4 = IO Figure 23. 20 VI = 3.8 V VO = 3 V o TA = 25 C Figure 24.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com DETAILED DESCRIPTION VRTC OUTPUT AND OPERATION WITH OR WITHOUT BACKUP BATTERY The VRTC pin is an always-on output, intended to supply up to 30 mA to a permanently required rail. This is the VCC_BATT rail of the Intel® PXA270 Bulverde processor for example. In applications using a backup battery, the backup voltage can be either directly connected to the TPS65022 VBACKUP pin if a Li-Ion cell is used, or via a boost converter (e.g.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 VSYSIN Vref V_VSYSIN priority #1 www.ti.com VCC VBACKUP Vref V_VBACKUP priority #2 V_VSYSIN V_VBACKUP EN VRTC LDO priority #3 VRTC Vref A. V_VSYSIN, V_VBACKUP thresholds: falling = 2.55 V, rising = 2.65 V ±3% B. RESPWRON thresholds: falling = 2.4 V, rising = 2.52 V ±3% RESPWRON Figure 25. STEP-DOWN CONVERTERS, VDCDC1, VDCDC2, and VDCDC3 The TPS65022 incorporates three synchronous step-down converters operating typically at 1.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com During PWM operation, the converters use a unique fast response voltage mode controller scheme with input voltage feed-forward to achieve good line and load regulation allowing the use of small ceramic input and output capacitors. At the beginning of each clock cycle initiated by the clock signal, the P-channel MOSFET switch is turned on. The inductor current ramps up until the comparator trips and the control logic turns off the switch.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com These control methods reduce the quiescent current to typically 14 μA per converter, and the switching activity to a minimum, thus achieving the highest converter efficiency. Setting the comparator thresholds at the nominal output voltage at light load current results in a low output voltage ripple. The ripple depends on the comparator delay and the size of the output capacitor.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com LOW DROPOUT VOLTAGE REGULATORS The low dropout voltage regulators are designed to operate well with low value ceramic input and output capacitors. They operate with input voltages down to 1.5 V. The LDOs offer a maximum dropout voltage of 300 mV at rated output current. Each LDO supports a current limit feature.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com SYSTEM RESET + CONTROL SIGNALS The RESPWRON signal can be used as a global reset for the application. It is an open drain output. The RESPWRON signal is generated according to the power good comparator of VRTC, and remains low for tnrespwron seconds after VRTC has risen above 2.52 V (falling threshold is 2.4 V, 5% hysteresis). tnrespwron is set by an external capacitor at the TRESPWRON pin. 1 nF gives typically 100 ms.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com TIMING DIAGRAMS HOT_RESET tDEGLITCH RESPWRON VO DCDC3 tNRESPWRON default voltage any voltage set 2 with I C interface Figure 26. HOT_RESET Timing VCC 1.9 V 0.8 V 2.35 V 1.9 V 1.2 V 2.47 V UVLO* 2.52 V VRTC 2.4 V 3V RESPWRON tNRESPWRON DCDCx_EN Ramp Within 800 ms VODCDCx 1.8 V slope depending on load LDO_EN VOLDOx 1.5 V *... Internal Signal VSYSIN = VBACKUP = GND; VINLDO = VCC Figure 27.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com VCC RESPWRON tNRESPWRON DCDC1_EN DCDC2_EN 3.3 V or 3 V VODCDC1 Ramp Within 800 ms VODCDC2 Ramp Within 800 ms 2.5 V or 1.8 V Ramp Within 800 ms DEFCORE register Default Value Set Higher Output Voltage for DCDC3 GO bit in CON_CTRL2 Cleared Automatically Automatically Set to Default Value DCDC3_EN VODCDC3 1.3 V or 1.55 V Ramp Within 800 ms 1.3 V or 1.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com whenever the clock line is high. There is one clock pulse per bit of data. Each data transfer is initiated with a start condition and terminated with a stop condition. When addressed, the TPS65022 device generates an acknowledge bit after the reception of each byte. The master device (microprocessor) must generate an extra clock pulse that is associated with the acknowledge bit.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com SCLK SDAT A6 Start A0 R/W ACK 0 0 R0 R7 A6 ACK A0 R/W ACK 1 0 0 Register Address Slave Address D0 D7 ACK Slave Drives the Data Slave Address Stop Master Drives ACK and Stop Repeated Start Note: SLAVE = TPS65020 Figure 32.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com PGOODZ.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com MASK.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com CON_CTRL.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com CON_CTRL2. Register Address: 05h (read/write) CON_CTRL2 Bit name and function Default Default value loaded by: Read/Write B7 B6 GO Core adj allowed 0 1 UVLO + DONE RESET(1) R/W R/W B5 0 Default Value: 40h B4 0 B3 B2 B1 B0 DCDC2 discharge DCDC1 discharge DCDC3 discharge 0 0 0 UVLO UVLO UVLO R/W R/W R/W 0 The CON_CTRL2 register can be used to take control the inductive converters.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com DEFCORE.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com LDO_CTRL.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com A more conservative approach is to select the inductor current rating just for the maximum switch current of the TPS65022 (2 A for the VDCDC1 and VDCDC2 converters, and 1.5 A for the VDCDC3 converter). The core material from inductor to inductor differs and has an impact on the efficiency especially at high switching frequencies. See Table 4 and the typical applications for possible inductors. Table 4.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com Table 5.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com VRTC Output The VRTC output is typically connected to the Vcc_Batt pin of a Intel® PXA270 processor. During power-up of the processor, the TPS65022 internally switches from the LDO or the backup battery to the system voltage connected at the VSYSIN pin (see Figure 25).It is required that a 4.7-μF (minimum) capacitor be added to the VRTC pin even if the output is not used.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com APPLICATION INFORMATION Layout Considerations As for all switching power supplies, the layout is an important step in the design. Proper function of the device demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If the layout is not carefully done, the regulators may show poor line and/or load regulation, and stability issues as well as EMI problems.
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TPS65022 SLVS667A – JULY 2006 – REVISED SEPTEMBER 2011 www.ti.com TYPICAL CONFIGURATION FOR THE Intel® PXA270 BULVERDE PROCESSOR Vcc_IO Vcc PWRFAIL 10 R nBatt_Fault Vcc 1 mF 10 mF 10 mF 10 mF LOW_BATT VINDCDC1 GPIOx VRTC Vcc_Batt DCDC2_EN VINDCDC2 SYS_EN DCDC1_EN VINDCDC3 VDCDC1 TPS65021 Vcc L1 2.2 mH PWRFAIL_SNS LOWBAT_SNS 2.2 mH Vcc_IO 3 V; 3.3 V Vcc_LCD 1.8 V; 2.5 V; 3 V; 3.3 V Vcc_BB 1.8 V; 2.5 V; 3 V; 3.3 V Vcc_MEM 1.8 V; 2.5 V; 3 V; 3.3 V Vcc_USIM 1.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TPS65022RHAR VQFN RHA 40 2500 330.0 16.4 6.3 6.3 1.1 12.0 16.0 Q2 TPS65022RHAT VQFN RHA 40 250 180.0 16.4 6.3 6.3 1.1 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS65022RHAR VQFN RHA 40 2500 367.0 367.0 38.0 TPS65022RHAT VQFN RHA 40 250 210.0 185.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.