Datasheet

CLK
DATA
STA STA STOSTO
t
h(STA)
t
(BUF)
t
(LOW)
t
r
t
f
t
h(DATA)
t
su(DATA)
t
su(STA)
t
h(STA)
t
su(STO)
t
(HIGH)
TPS65020
www.ti.com SLVS607C –SEPTEMBER 2005– REVISED SEPTEMBER 2011
Figure 35. Serial i/f Timing Diagram
MIN MAX UNIT
f
MAX
Clock frequency 400 kHz
t
wH(HIGH)
Clock high time 600 ns
t
wL(LOW)
Clock low time 1300 ns
t
R
DATA and CLK rise time 300 ns
t
F
DATA and CLK fall time 300 ns
t
h(STA)
Hold time (repeated) START condition (after this period the first clock pulse is generated) 600 ns
t
h(DATA)
Setup time for repeated START condition 600 ns
t
h(DATA)
Data input hold time 300 ns
t
su(DATA)
Data input setup time 300 ns
t
su(STO)
STOP condition setup time 600 ns
t
(BUF)
Bus free time 1300 ns
VERSION. Register Address: 00h (read only)
VERSION B7 B6 B5 B4 B3 B2 B1 B0
Bit name and 0 0 0 1 1 0 0 1
function
Read/Write R R R R R R R R
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