Datasheet
TPS65020
SLVS607C –SEPTEMBER 2005– REVISED SEPTEMBER 2011
www.ti.com
This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with
appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.
ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more
susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.
ORDERING INFORMATION
T
A
PACKAGE
(1)
PART NUMBER
(2)
–40°C to 85°C 40 pin QFN (RHA) TPS65020RHA
(1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI
Web site at www.ti.com.
(2) The RHA package is available in tape and reel. Add the R suffix (TPS65020RHAR) to order quantities of 2500 parts per reel. Add the T
suffix (TPS65020RHAT) to order quantities of 250 parts per reel.
ABSOLUTE MAXIMUM RATINGS
(1)
over operating free-air temperature range (unless otherwise noted)
VALUE UNIT
V
I
Input voltage range on all pins except AGND and PGND pins with respect to AGND –0.3 to 7 V
Current at VINDCDC1, L1, PGND1, VINDCDC2, L2, PGND2, VINDCDC3, L3, PGND3 2000 mA
Peak current at all other pins 1000 mA
Continuous total power dissipation See Dissipation Rating Table
T
A
Operating free-air temperature –40 to 85 °C
T
J
Maximum junction temperature 125 °C
T
stg
Storage temperature –65 to 150 °C
(1) Stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. These are stress ratings
only and functional operation of the device at these or any other conditions beyond those indicated under recommended operating
conditions is not implied. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability
THERMAL INFORMATION
TPS65020
THERMAL METRIC
(1)
RHA UNITS
40 PINS
θ
JA
Junction-to-ambient thermal resistance 31.6
θ
JCtop
Junction-to-case (top) thermal resistance 18.2
θ
JB
Junction-to-board thermal resistance 6.6
°C/W
ψ
JT
Junction-to-top characterization parameter 0.2
ψ
JB
Junction-to-board characterization parameter 6.5
θ
JCbot
Junction-to-case (bottom) thermal resistance 1.7
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
RECOMMENDED OPERATING CONDITIONS
over operating free-air temperature range (unless otherwise noted)
MIN NOM MAX UNIT
Input voltage range step-down convertors and Vcc pin
V
CC
(VINDCDC1, VINDCDC2, VINDCDC3, Vcc); pins need to be tied to the same 2.5 6 V
voltage rail
Output voltage range for VDCDC1 step-down convertor
(1)
0.6 VINDCDC1
V
O
Output voltage range for VDCDC2 step-down convertor
(1)
0.6 VINDCDC2 V
Output voltage range for VDCDC3 (core) step-down convertor
(1)
0.6 VINDCDC3
V
I
Input voltage range for LDOs (VINLDO1, VINLDO2) 1.5 6.5 V
V
O
Output voltage range for LDOs (VLDO1, VLDO2) 1 VINLDO1-2 V
I
O(DCDC1)
Output current at L1 1200 mA
(1) When using an external resistor divider at DEFDCDC3, DEFDCDC2, DEFDCDC1
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