Datasheet

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SERIAL INTERFACE TIMING REQUIREMENTS
PIN ASSIGNMENTS
ISET
TS
BATT_COVER
AC
VBAT_A
VBAT_B
USB
AGND2
AGND3
PGND2
PB_ONOFF
VCORE
RGZ PACKAGE
(TOP VIEW)
37
38
39
40
41
42
43
44
45
46
47
48
24
23
22
21
20
19
18
17
16
15
14
13
1 2 3 4 5 6 7 8 9 10 11 12
36 35 34 33 3231 30 29 28 27 26 25
LOW_PWR
INT
PWRFAIL
RESPWRON
MPU_RESET
HOT_RESET
SCLK
IFLSB
TPOR
GPIO1 GPIO2
SDAT
VLDO1
VFB_LDO1
VINLDO1
AGND1
VLDO2
VINLDO2
GPIO3
GPIO4
PGND1_B
PGND1_A
PS_SEQ
VMAIN
DEFCORE
LED2
VIB
L2
VINCORE
VCC
VINMAIN_A VINMAIN_B
L1_A L1_B
PG
DEFMAIN
NC − No internal connection
TPS65013
SLVS517A – AUGUST 2004 – REVISED JANUARY 2005
MIN MAX UNIT
Clock frequency, f
MAX
400 kHz
Clock high time, t
wH(HIGH)
600 ns
Clock low time, t
wL(LOW)
1300 ns
DATA and CLK rise time, t
R
300 ns
DATA and CLK fall time, t
F
300 ns
Hold time (repeated) START condition (after this period the first clock pulse is generated), t
h(STA)
600 ns
Setup time for repeated START condition, t
h(DATA)
600 ns
Data input hold time, t
h(DATA)
0 ns
Data input setup time, t
su(DATA)
100 ns
STOP condition setup time, t
su(STO)
600 ns
Bus free time, t
(BUF)
1300 ns
9