Datasheet

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I
RMSC(out)
 V
O

1–
V
O
V
I
L  ƒ

1
2  3

(5)
V
O
 V
O

1–
V
O
V
I
L  ƒ


1
8  C
O
 ƒ
 ESR

(6)
Input Capacitor Selection
LDO1
Output Voltage Adjustment
TPS65013
SLVS517A – AUGUST 2004 – REVISED JANUARY 2005
If ceramic output capacitors are used, the capacitor RMS ripple current rating always meets the application
requirements. Just for completeness the RMS ripple current is calculated as:
At nominal load current, the inductive converters operate in PWM mode and the overall output voltage ripple is
the sum of the voltage spike caused by the output capacitor ESR plus the voltage ripple caused by charging and
discharging the output capacitor:
Where the highest output voltage ripple occurs at the highest input voltage V
I
.
At light load currents, the converters operate in power-save mode and the output voltage ripple is independent of
the output capacitor value. The output voltage ripple is set by the internal comparator thresholds. The typical
output voltage ripple is 1% of the nominal output voltage. If the output voltage for the core converter is
programmed to its lowest voltage of 0.85 V, the output capacitor must be increased to 22 µF for low output
voltage ripple. This is because the current in the inductor decreases slowly during the off-time and further
increases the output voltage even when the PMOS is off. This effect increases with low output voltages.
A pulsating input current is the nature of the buck converter. Therefore, a low ESR input capacitor is required for
best input voltage filtering. It also minimizes the interference with other circuits caused by high input voltage
spikes. The main converter needs a 22-µF ceramic input capacitor and the core converter a 10-µF ceramic
capacitor. The input capacitor for the main and the core converter can be combined and one 22-µF capacitor can
be used instead, because the two converters operate with a phase shift of 270 degrees. The input capacitor can
be increased without any limit for better input voltage filtering. The VCC pin should be separated from the input
for the main and the core converter. A filter resistor of up to 100 Ω and a 1-µF capacitor is used for decoupling
the VCC pin from switching noise.
Table 5. Possible Capacitors
CAPACITOR VALUE CASE SIZE COMPONENT SUPPLIER COMMENTS
22 µF 1206 TDK C3216X5R0J226M Ceramic
22 µF 1206 Taiyo Yuden JMK316BJ226ML Ceramic
22 µF 1210 Taiyo Yuden JMK325BJ226MM Ceramic
The output voltage of LDO1 is set with a resistor divider at the feedback pin. The sum of the two resistors must
not exceed 1 M Ω to minimize voltage changes due to leakage current into the feedback pin. The output voltage
for LDO1 after start-up is the voltage set by the external resistor divider. It can be reprogrammed with the I
2
C
interface to the three other values defined in the register VREGS1.
50