Datasheet

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VDCDC2 Register (Address: 0Dh—Default Value: 48h/78h)
TPS65013
SLVS517A – AUGUST 2004 – REVISED JANUARY 2005
UVLO1 UVLO0 V
UVLO
0 0 2.5 V
0 1 2.75 V
1 0 3.0 V
1 1 3.25 V
Bit 4 - ENABLE SUPPLY (selects between LOW-POWER mode and WAIT mode):
• 0 = WAIT mode allowed, activated when LOW_PWR pin = 1 and VDCDC1 < 3 >= 1.
• 1 = The TPS65013 enters LOW-POWER mode when LOW_PWR pin = 1 and VDCDC1 < 3 >= 1.
Bit 3 - ENABLE LP:
• 0 = disables the low-power function of the LOW_PWR pin.
• 1 = enables the low-power function of the LOW_PWR pin.
Bit 2 - MAIN DISCHARGE:
• 0 = disable the active discharge of the VMAIN converter output.
• 1 = enable the active discharge of the VMAIN converter output, when the converter is disabled (i.e., in WAIT
mode).
Bit 1-Bit 0 - MAIN<1:0>: The VMAIN converter output voltages are set according to the following table, with the
default values in bold set by the DEFMAIN pin. The default voltage can subsequently be over written via the
serial interface after start-up.
MAIN1 MAIN0 VMAIN
0 0 3.0 V
0 1 2.75 V
1 0 1.8 V
1 1 3.3 V
VDCDC2 B7 B6 B5 B4 B3 B2 B1 B0
CORE
Bit name LP_COREOFF CORE2 CORE1 CORE0 CORELP0 CORELP1 VIB
DISCHARGE
Default 0 1 DEFCORE DEFCORE 1 0 0 0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
The VDCDC2 register is used to program the VCORE switching converter output voltage. It is programmable in 8
steps between 0.85 V and 1.6 V. The default value is governed by the DEFCORE pin; DEFCORE=0 sets an
output voltage of 1.3 V. DEFCORE=1 sets an output voltage of 1.6 V.
Bit 7 - LP_COREOFF:
• 0 = VCORE converter is enabled in low-power mode.
• 1 = VCORE converter is disabled in low-power mode.
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