Datasheet
www.ti.com
LED2_ON Register (Address: 0Ah—Default Value: 00h)
LED2_PER (Register Address: 0Bh—Default Value: 00h)
VDCDC1 Register (Address: 0Ch—Default Value: 32h/33h)
TPS65013
SLVS517A – AUGUST 2004 – REVISED JANUARY 2005
Bit 7 - PG2: Control of the PG pin is determined by PG1 and PG2 according to the following table. Default shown
in bold.
PG1 PG2 BEHAVIOR OF PG OPEN-DRAIN OUTPUT
0 0 Under charger control
0 1 Blink
1 0 Off
1 1 Always On
Bit 6-Bit 0 - LED1_PER<6:0> are used to program the time period of the open-drain output transistor at the PG
pin. The minimum period is typically 100 ms and one LSB corresponds to a 100-ms step change in the period.
LED2_ON B7 B6 B5 B4 B3 B2 B1 B0
Bit name LED21 LED2 ON6 LED2 ON5 LED2 ON4 LED2 ON3 LED2 ON2 LED2 ON1 LED2 ON0
Default 0 0 0 0 0 0 0 0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
The LED2_ON and LED2_PER registers are used to control the LED2 open-drain output.
Bit 7 LED22: Control is determined by LED21 and LED22 according to the table under LED2_PER register.
Bit 6-Bit 0 - LED2_ON<6:0> are used to program the on-time of the open-drain output transistor at the LED2 pin.
The minimum on-time is typically 10 ms and one LSB corresponds to a 10-ms step change in the on-time.
LED2_PER B7 B6 B5 B4 B3 B2 B1 B0
Bit name LED22 LED2 PER6 LED2 PER5 LED2 PER4 LED2 PER3 LED2 PER2 LED2 PER1 LED2 PER 0
Default 0 0 0 0 0 0 0 0
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
Bit 7 LED22: Control is determined by LED21 and LED22 according to the table. Default shown in bold.
Bit 6-Bit 0 - LED2_ON<6:0> are used to program the on-time of the open-drain output transistor at the LED2 pin.
The minimum on-time is typically 100 ms and one LSB corresponds to a 100-ms step change in the on-time.
LED21 LED22 BEHAVIOR OF LED2 OPEN-DRAIN OUTPUT
0 0 Off
0 1 Blink
1 0 Off
1 1 Always On
VDCDC1 B7 B6 B5 B4 B3 B2 B1 B0
Bit name FPWM UVLO1 UVLO0 ENABLE ENABLE MAIN DIS- MAIN1 MAIN0
SUPPLY LP CHARGE
Default 0 0 1 1 0 0 1 DEFMAIN
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
The VDCDC1 register is used to program the VMAIN switching converter.
Bit 7 - FPWM: forced PWM mode for dc-dc converters.
• 0 = MAIN and the CORE dc-dc converter are allowed to switch into PFM mode.
• 1 = MAIN and the CORE dc-dc converter operate with forced fixed frequency PWM mode and are not
allowed to switch into PFM mode, at light load.
Bit 6-Bit 5 - UVLO<1:0>: The undervoltage threshold voltage is set by UVLO1 and UVLO0 according to the
following table, with the default value in bold.
45