Datasheet

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MASK2 Register (Address: 04h—Default Value: FFh)
ACKINT1 Register (Address: 05h—Default Value: 00h)
ACKINT2 Register (Address: 06h—Default Value: 00h)
CHGCONFIG Register Address: 07h—Default Value: 1Bh
TPS65013
SLVS517A – AUGUST 2004 – REVISED JANUARY 2005
MASK2 B7 B6 B5 B4 B3 B2 B1 B0
Mask Mask Mask PGOOD Mask PGOOD Mask PGOOD
Bit name Mask UVLO NO_CH Mask PGOOD CORE
PB_ONOFF BATT_COVER LDO2 LDO1 MAIN
Default 1 1 1 1 1 1 1 1
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
The MASK2 register is used to mask all or any of the conditions in the corresponding REGSTATUS<7:0>
positions being indicated at the INT pin. Default is to mask all.
ACKINT1 B7 B6 B5 B4 B3 B2 B1 B0
Ack Thermal Ack
Bit name Ack USB Ack AC Ack Term Ack Taper Ack Chg Ack Prechg
Shutdown BattTemp
Default 0 0 0 0 0 0 0 0
Read/write R R R R R R R R
The ACKINT1 register is internally used to acknowledge any of the interrupts in the corresponding
CHGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT
pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes
high, else it will remain low. A 1 at any position in ACKINT1 is automatically cleared when the corresponding
interrupt condition in CHGSTATUS is removed. The application processor should not normally need to access
the ACKINT1 register.
ACKINT2 B7 B6 B5 B4 B3 B2 B1 B0
Ack Ack BATT_ Ack PGOOD Ack PGOOD Ack PGOOD Ack PGOOD
Bit name Ack UVLO Ack NO_CH
PB_ONOFF COVER LDO2 LDO1 MAIN CORE
Default 0 0 0 0 0 0 0 0
Read/write R R R R R R R R
The ACKINT2 register is internally used to acknowledge any of the interrupts in the corresponding
REGSTATUS<7:0> positions. When this is done, the acknowledged interrupt is no longer fed through to the INT
pin and so the INT pin becomes free to indicate the next pending interrupt. If none exists, then the INT pin goes
high, else it will remain low. A 1 at any position in ACKINT2 is automatically cleared when the corresponding
interrupt condition in REGSTATUS is removed. The application processor should not normally need to access
the ACKINT2 register.
CHGCONFIG B7 B6 B5 B4 B3 B2 B1 B0
Fast charge
MSB charge LSB charge USB / 100 USB charge Charge
Bit name AUA Charger reset timer + taper
current current mA 500 mA allowed enable
timer enabled
Default 0 0 0 1 1 0 1 1
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
The CHGCONFIG register is used to configure the charger.
Bit 7 - AUA:
• 0 = If a voltage is present at AC or USB in the appropriate range for charging, and if V
CC
> UVLO, the
TPS65013 is forced into ON mode. The WAIT mode is disabled.
• 1 = If a voltage source at AC or USB is present, the WAIT mode is enabled, and the TPS65013 does not
automatically turn on the converters.
Bit 6 - Charger reset:
• Clears all the timers in the charger and forces a restart of the charge algorithm.
• 0 / 1 = This bit must be set and then reset via the serial interface.
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