Datasheet

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REGSTATUS Register (Address: 02h—Default Value: 00h)
MASK1 Register (Address: 03h—Default Value: FFh)
TPS65013
SLVS517A – AUGUST 2004 – REVISED JANUARY 2005
REGSTATUS B7 B6 B5 B4 B3 B2 B1 B0
PGOOD PGOOD PGOOD PGOOD
Bit name PB_ONOFF BATT_COVER UVLO NO_CH
LDO2 LDO1 MAIN CORE
Default 0 0 0 0 0 0 0 0
Read/write R R R R R R R R
Bit 7 - PB_ONOFF:
• 0 = inactive
• 1 = user activated the PB_ONOFF switch to request that all rails are shut down.
Bit 6 - BATT_COVER:
• 0 = BATT_COVER pin is high.
• 1 = BATT_COVER pin is low.
Bit 5 - UVLO:
• 0 = voltage at the VCC pin above UVLO threshold.
• 1 = voltage at the VCC pin has dropped below the UVLO threshold.
Bit 4 - NO_CH:
• 0 = one or more charging sources are present (voltage at AC and/or USB applied).
• 1 = no charging source is present.
Bit 3 - PGOOD LDO2:
• 0 = LDO2 output in regulation, or LDO2 disabled with VREGS1 < 7 > = 0
• 1 = LDO2 output out of regulation.
Bit 2 - PGOOD LDO1:
• 0 = LDO1 output in regulation, or LDO1 disabled with VREGS1 < 3 > = 0
• 1 = LDO1 output out of regulation.
Bit 1 - PGOOD MAIN:
• 0 = Main converter output in regulation.
• 1 = Main converter output out of regulation.
Bit 0 - PGOOD CORE:
• 0 = Core converter output in regulation.
• 1 = Core converter output out of regulation, or VDCDC2 < 7 > = 1 in low-power mode
A rising edge in the REGSTATUS register contents causes INT to be driven low if it is not masked in the MASK2.
MASK1 B7 B6 B5 B4 B3 B2 B1 B0
Mask Thermal Mask
Bit name Mask USB Mask AC Mask Term Mask Taper Mask Chg Mask Prechg
Suspend BattTemp
Default 1 1 1 1 1 1 1 1
Read/write R/W R/W R/W R/W R/W R/W R/W R/W
The MASK1 register is used to mask all or any of the conditions in the corresponding CHGSTATUS<7:0>
positions being indicated at the INT pin. Default is to mask all.
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