VCORE
VMAIN
VLDO1
VLDO2
95% VCORE
95% VLDO2
HOT_RESET
HOT_RESET
DEGLITCH
INT
MPU_RESET
t
(GLITCH)
t(
MPU_RESET)
TPS65013
SLVS517A – AUGUST 2004 – REVISED JANUARY 2005
Figure 37. State 3 to State 2 Transition ( HOT_RESET Activated, See Interrupt Management Section for INT
Behavior)
35
