Datasheet

www.ti.com
98%
VCORE
95%
VMAIN
*.... internal signal
t
(GLITCH)
t
n(RESPWRON)
V
CC
BATT
COVER
BATT COVER
DEG*
PB_ONOFF
REFSYS
EN*
UVLO*
ENABLE
SUPPLIES*
VCORE
VMAIN
VLDO1
VLDO2
RESPWRON
MPU_RESET
PWREFAIL
INT
t
(GLITCH)
TPS65013
SLVS517A – AUGUST 2004 – REVISED JANUARY 2005
Figure 32. State 1 to State 2 Transition (PS_SEQ=0, V
CC
> V
UVLO
+ HYST)
Valid for LDO1 supplied from VMAIN as described earlier in this Application Section.
If 2.4 ms after application, V
CC
is still below the default UVLO threshold (3.15 V for V
CC
rising), then start-up is as
shown in Figure 33 .
30