Datasheet

www.ti.com
TPS65013
SLVS517A – AUGUST 2004 – REVISED JANUARY 2005
Table 2. TPS65013 Possible Configurations
CONVERTER MAIN CORE LDO1 LDO2
LOW-POWER mode 1 0/1 0/1 0/1
WAIT mode 0 0 0/1 0/1
• 0 = converter is disabled
• 1 = converter is enabled
Table 3 indicates the typical quiescent current consumption in each power state.
Table 3. TPS65013 Typical Current Consumption
TOTAL QUIESCENT
STATE QUIESCENT CURRENT BREAKDOWN
CURRENT
1 0
2 30 µA - 70 µA VMAIN (12 µA) + VCORE (12 µA) + LDOs (20 µA each, max 2) + UVLO + reference +
PowerGood
3 30 µA - 55 µA VMAIN (12 µA) + VCORE (12 µA) + LDOs (10 µA each, max 2) + UVLO + reference +
PowerGood
4 13 µA UVLO + reference circuitry
29