Datasheet

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No
Monitored Permanently
*1: All registers are reset to their default values in WAIT Mode.
*2: ENABLE_LP bit, VDCDC1 <3> Must be set.
if AC or USB power is present, AUA bit, CHGCONFIG <7> must also be set.
*3: ENABLE_SUPPLY bit, VDCDC1 <4> must be cleared.
ENABLE_LP bit, VDCDC1 <3> must be set.
LDO2OFF/SLP and LDO1OFF/SLP <6,2> must be set or LDOs and voltage
reference remain enabled and registers not reset.
if AC or USB power is present, AUA bit, CHGCONFIG <7> must also be set.
ENABLE_LP default: cleared
ENABLE_SUPPLY default: set
AUA default: cleared
LDO1OFF/SLP default: cleared
LDO2OFF/SLP
default: cleared
Yes
No
TPS65011
RESPWRON,
PWRFAIL, INT,
MPU_RESET Low.
Reset
RESPWRON Timer
VMAIN
Voltage
Enabled and
Good?
Start
RESPWRON
Timer if Not Running
RESPWRON
Timer Done ?
Yes
Release
RESPWRON,
PWRFAIL, INT,
MPU_RESET
1
No
0
Boot VMAIN
Converter + LDOs
Boot VCORE
Converter
LOW_
POWER
Mode
LOW_PWR
De-asserted,
PB_ONOFF
Button Pressed
LOW_PWR
Asserted *2
HOT_RESET
Button Pressed
No
Yes
VCORE Voltage
Good ?
No
Set MPU_RESET
Low, Start
MPU_RESET Timer
MPU_RESET
Timer Done ?
Yes
Processor Initiated
Shutdown *3
ON
Shutdown VCORE,
VMAIN + LDOs
According to
PS_SEQ
Yes
VCC>UVLO ?
BATT_COVER
High ?
No
No
Yes
UVLO_TEMP
Timer Done ?
Set PWRFAIL Low,
Start UVLO_TEMP
Timer if Not Running
No
VCC>UVOL,
T
j
<Tshtdwn,
BATT_COVER
High ?
Yes
Yes
Monitored Permanently
AC and/or USB
Power Applied.
No
Power
Main Battery Power
Applied
WAIT
*1
AC and/or USB
Power Applied
or
PB_ONOFF or
HOT_RESET
Button Pressed.
VCC>UVLO ?
BATT_COVER
High ?
Value
PS_SEQ ?
Boot VCORE
Converter + LDOs
Boot VMAIN
Converter
Release
MPU_RESET
TPS65013
SLVS517A – AUGUST 2004 – REVISED JANUARY 2005
Figure 31 shows the state diagram for the TPS65013 power sequencing. The charger function is not shown in
the state diagram since this function is independent of these states.
Figure 31. TPS65013 Power-On State Diagram
27