Datasheet

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POWER-UP SEQUENCING
TPS65013
SLVS517A – AUGUST 2004 – REVISED JANUARY 2005
The TPS65013 power-up sequencing is designed to allow the maximum flexibility without generating excessive
logistical or system complexity. The relevant control pins are described in the following table:
Table 1. Control Pins
PIN NAME INPUT/OUTPUT FUNCTION
Input signal indicating power-up and power-down sequence of the switching converters. PS_SEQ = 0
PS_SEQ I forces the core regulator to ramp up first and down last. PS_SEQ = 1 forces the main regulator to ramp up
first and down last.
Defines the default voltage of the VCORE switching converter. DEFCORE = 0 defaults VCORE to 1.3 V,
DEFCORE I
DEFCORE = VCC defaults VCORE to 1.6 V.
Defines the default voltage of the VMAIN switching converter. DEFMAIN = 0 defaults VMAIN to 1.8 V,
DEFMAIN I
DEFMAIN = VCC defaults VMAIN to 3.3 V.
The LOW_PWR pin is used to lower VCORE to the preset voltage in the VDCDC2 register when the
processor is in deep-sleep mode. Alternatively, VCORE can be disabled in low-power mode if the
LP_COREOFF bit is set in the VDCDC2 register. LOW_PWR is ignored if the ENABLE LP bit is not set in
the VDCDC1 register. The TPS65013 uses the rising edge of the internal signal formed by a logical AND
of LOW_PWR and ENABLE LP to enter low-power mode. TPS65013 is forced out of low-power mode by
LOW_PWR I
de-asserting LOW_PWR, by resetting ENABLE LP to 0, by activating the PB_ONOFF pin or by activating
the HOT_RESET pin. There are two ways to get the device back into low-power mode: a) toggle the
LOW_PWR pin, or b) toggle the low-power bit when the LOW_PWR pin is held high. The LOW_PWR pin
is also used to set the TPS65013 into WAIT mode. If USB or AC is present, the AUA bit (CHCONFIG<7>)
must be set to enter the WAIT mode, see Figure 31 .
PB_ONOFF can be used to exit the low-power mode and return the core voltage to the value before
low-power mode was entered. If PB_ONOFF is used to exit the low-power mode, then the low-power
PB_ONOFF I mode can be reentered by toggling the LOW_PWR pin or by toggling the low-power bit when the
LOW_PWR pin is held high. A 1-M Ω pulldown resistor is integrated in TPS65013. PB_ONOFF is internally
de-bounced by the TPS65013. A maskable interrupt is generated when PB_ONOFF is activated.
The HOT_RESET pin has a similar functionality to the PB_ONOFF pin. In addition, it generates a reset
( MPU_RESET) for the MPU when the VCORE voltage is in regulation. HOT_RESET does not alter any
HOT_RESET I
TPS65013 settings unless low-power mode was active, in which case it is exited. A 1-M Ω pullup resistor
to V
CC
is integrated in TPS65013. HOT_RESET is internally de-bounced by the TPS65013.
The BATT_COVER pin is used as an early warning that the main battery is about to be removed.
BATT_COVER = V
CC
indicates that the cover is in place, BATT_COVER = 0 indicates that the cover is not
in place. TPS65013 generates a maskable interrupt when the BATT_COVER pin goes low. PWRFAIL is
BATT_COVER I also held low when BATT_COVER goes low. This feature may be disabled by tying BATT_COVER
permanently to VCC. The TPS65013 shuts down the main and the core converter and sets the LDOs into
low-power mode. A 2-M Ω pulldown resistor is integrated in the TPS65013 at the BATT_COVER pin.
BATT_COVER is internally de-bounced by the TPS65013.
RESPWRON is held low while the switching converters (and any LDO's defined as default on) are starting
up. It is determined by the state of MAIN's output voltage; when the voltage is higher than the power-good
RESPWRON O
comparator threshold, then RESPWRON is high, when VMAIN is low, then RESPWRON is low.
RESPWRON is held low for t
n(RESPWRON)
seconds after VMAIN has settled.
MPU_RESET can be used to reset the processor if the user activates the HOT_RESET button. The
MPU_RESET O MPU_RESET output is active for t
(MPU_nRESET)
seconds. It also forces TPS65013 to leave low-power
mode. MPU_RESET is also held low as long as RESPWRON is held low.
PWRFAIL indicates when V
CC
< V
(UVLO)
, when the TPS65013 is about to shut down due to an internal
PWRFAIL O overtemperature condition or when BATT_COVER is low. PWRFAIL is also held low as long as
RESPWRON is held low.
TPOR is used to set the delay time for the RESPWRON reset signal.
TPOR I
TPOR = 0 sets the delay time to 100 ms. TPOR = 1 sets the delay time to 1 s.
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