Datasheet

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SCL
SDA
SCLK
SDATAGND PGND
VFB_LDO1
VLDO1
DDRAM, Flash
@1.8V
VLDO2
VDDSHV1, VDDSHV2,
VDDSHV4, VDDSHV5,
VDDSHV10
Camera,
LCD...
VMAIN
L1
Vbat
L2
VCORE
VDDA (1.3V)
VDD, VDD1, VDD2,
VDD4, VDD_DLL
EN_LDO2
LOW_PWR LOW_PWR
BVLZ
DIGIO
ON_/OFF
WAKEUP_IT
Vbat
IFLSB
PS_SEQ
DEFMAIN
DEFCORE
Vbat
1.3V
VINCORE
VINMAIN
VINLDO1
VINLDO2
Vcc
Vbat
PB_ONOFF
TPOR
BAT_COVERVbat
ISET
AC
USB
Vbat
TS
BATT+
BATT−
TEMP
AC Adapter
1.8V
VDD_RTC (1.3V)
LDO 1
TPS79301
EN_LDO1
3.3V
1.8V
GPIO1
GPIO2
VLDO2
USB Power
Vbat
LDO 2
TPS79301
INT
PWRFAIL
RESPWRON
MPU_RESET
HOT_RESET
RESPWRON
MPU_RESET
TPS65013 OMAP1710
TPS65013
SLVS517A – AUGUST 2004 – REVISED JANUARY 2005
APPLICATION INFORMATION (continued)
Supply LDO1 from VMAIN as shown in Figure 25 . If this is not done, then subsequent to a UVLO, OVERTEMP,
or BATT_COVER = 0 condition, the RESPWRON signal goes high before the VCORE rail has ramped and
stabilized. Therefore, the processor core does not receive a power-on-reset signal.
Figure 26. Typical Application Circuit for OMAP1710
18