Datasheet

TPS65000, TPS65001, TPS650001
TPS650003, TPS650006, TPS650061
SLVS810B –JUNE 2009–REVISED AUGUST 2010 www.ti.com
ELECTRICAL CHARACTERISTICS (continued)
Over full operating ambient temperature range, typical values are at T
A
= 25° C. Unless otherwise noted, specifications apply
for condition V
IN
= EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 mH, C
OUT
= 10 mF, C
IN
= 4.7 mF, (see the
parameter measurement information).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
SUPPLY CURRENT TPS65001
MODE low, EN_DCDC high,
EN_LDO1/2 low, 24 37 mA
I
OUT
= 0 mA and no switching
MODE low, EN_DCDC low,
I
Q
Operating quiescent current
EN_LDO1/2 high, I
OUT
= 0mA 55 62 mA
I
OUT
= 0 mA and no switching
(3)
EN_DCDC high, MODE high,
4 mA
EN_LDO1/2 low, I
OUT
= 0mA
I
SD
Shutdown Current EN_DCDC low EN_LDO1 and EN_LDO2 low 11 17 mA
DIGITAL PINS (EN_DCDC, EN_LDO1, EN_LDO2, MODE, PG, MR, RST
V
IH
High level input voltage 1.2 V
V
IL
Low level input voltage 0.4 V
V
OL
Low level output voltage PG and RST pins only, I
O
= -100mA 0.4 V
MODE, EN_DCDC, EN_LDO1, EN_LDO2 tied to
I
lkg
Input leakage current 0.01 0.1 mA
GND or VINDCDC
OSCILLATOR
f
SW
Oscillator frequency 1.722 2.25 2.847 MHz
STEP DOWN CONVERTER POWER SWITCH
High side MOSFET on-resistance 240 480
R
DS(on)
VINDCDC = V
GS
= 3.6V mΩ
Low side MOSFET on-resistance 185 380
2.3 V ≤ VINDCDC ≤ 2.5V 300
I
O
DC output current mA
2.5 V ≤ VINDCDC ≤ 6V 600
DC output current (TPS650061 1000
I
O
2.7 V ≤ VINDCDC ≤ 6V mA
ONLY)
Forward current limit PMOS and
I
LIMF
2.3 V ≤ VINDCDC ≤ 6V 800 1000 1400 mA
NMOS
Forward current limit PMOS and
I
LIMF
2.7 V ≤ VINDCDC ≤ 6V 1200 1500 1680 mA
NMOS (TPS650061 ONLY)
Thermal shutdown Increasing junction temperature 150
T
SD
°C
Thermal shutdown hysteresis Decreasing junction temperature 30
STEP DOWN CONVERTER OUTPUT VOLTAGE
Adjustable output voltage range,
VDCDC 0.6 VINDCDC V
DCDC
FB_DCDC pin current 0.1 mA
V
ref
Internal reference voltage 0.594 0.6 0.606 V
Output Voltage Accuracy (PWM MODE = high,
–1.5% 0% 1.5%
Mode)
(4)
2.3 ≤ VINDCDC ≤ 6V
VDCDC
Output Voltage Accuracy (PFM MODE low
1%
mode)
(5)
+1% voltage positioning active
Load regulation (PWM mode) MODE high 0.5 %/A
t
Start
Start-up time EN_DCDC to start of switching (10%) 250 ms
t
Ramp
VDCDC ramp up time VDCDC ramp from 10% to 90% 250 ms
Internal discharge resistance at EN_DCDC low
R
DIS
450 Ω
SW
(3) The max quiescent current of enabling LDOs is 8mA higher for TPS650001, TPS650003, TPS650006 and TPS650061.
(4) For VINDCDC = VDCDC + 1V
(5) In PFM Mode, the internal reference voltage is typ 1.01 × V
REF
.
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