Datasheet

TPS65000, TPS65001, TPS650001
TPS650003, TPS650006, TPS650061
www.ti.com SLVS810B –JUNE 2009–REVISED AUGUST 2010
DISSIPATION RATINGS
T
A
≤ 25°C T
A
= 70°C T
A
= 85°C
DEVICE PACKAGE R
qJA
R
qJB
POWER RATING POWER RATING POWER RATING
TPS65000/01
(1)
270°C/W 14°C/W 370 mW 204 mW 148 mW
RTE / RUK
TPS65000/01
(2)
48.7°C/W 14°C/W 2.05 W 1.13 W 821 mW
(1) The JEDEC low-K (1s) board used to derive this data was a 3in × 3in, two-layer board with 2-ounce copper traces on top of the board.
(2) The JEDEC high-K (2s2p) board used to derive this data was a 3in × 3in, multilayer board with 1-ounce internal power and ground.
RECOMMENDED OPERATING CONDITIONS
MIN NOM MAX UNIT
L1 SW pin inductor 1.5 2.2 3.3 mH
Input capacitor at VINDCDC 10 mF
C
I
Input capacitor at VINLDO1/2 2.2 mF
Output capacitor for DCDC 10 22 mF
C
O
Output capacitor for LDO1/2 2.2 mF
DCDC converter output current 600 mA
DCDC converter output current (TPS650061 ONLY) 1000 mA
I
O
LDO1 output current 300 mA
LDO2 output current 300 mA
T
A
Operating ambient temperature -40 85 °C
ELECTRICAL CHARACTERISTICS
Over full operating ambient temperature range, typical values are at T
A
= 25° C. Unless otherwise noted, specifications apply
for condition V
IN
= EN_LDOx = EN_DCDC = 3.6 V. External components L = 2.2 mH, C
OUT
= 10 mF, C
IN
= 4.7 mF, (see the
parameter measurement information).
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
OPERATING VOLTAGE
Input voltage for VINDCDC of 2.3 6
DCDC converter
V
IN
V
Input voltage for LDO1 (VINLDO1) See
(1)
1.6 6
Input voltage for LDO2 (VINLDO2) See
(1)
1.6 6
Internal undervoltage lockout
V
CC
falling 1.72 1.77 1.82 V
threshold
UVLO
Internal undervoltage lockout
160 mV
hysteresis
SUPPLY CURRENT TPS65000
MODE low, EN_DCDC high,
EN_LDO1/2 low, 23 32
I
OUT
= 0 mA and no switching
mA
MODE low, EN_DCDC low,
I
Q
Operating quiescent current
EN_LDO1/2 high, I
OUT
= 0mA 50 57
I
OUT
= 0 mA and no switching
(2)
EN_DCDC high, MODE high,
4 mA
EN_LDO1/2 low, I
OUT
= 0mA
I
SD
Shutdown Current EN_DCDC low EN_LDO1 and EN_LDO2 low 0.16 2.2 mA
(1) The design principle allows only VINDCDC to be the highest supply in the system if different voltage input supplies separately to DCDC
converter and LDOs, meaning VINDCDC ≥ VINLDO1, VINDCDC ≥ VINLDO2.
(2) The max quiescent current of enabling LDOs is 8mA higher for TPS650001, TPS650003, TPS650006 and TPS650061.
Copyright © 2009–2010, Texas Instruments Incorporated Submit Documentation Feedback 3
Product Folder Link(s): TPS65000 TPS65001 TPS650001 TPS650003 TPS650006 TPS650061