Datasheet

( )
S2 S1
RST
S2
R + R
V = 0.6V x
R
RST
-6
C
t = 0.6V x
2 x 10 A
RST
Reset Trigger
0
1
GND
Hi-Z
I
TRST
0
2 Am
V
TRST
GND
0.6V
t
RST
t
RST
TPS65000, TPS65001, TPS650001
TPS650003, TPS650006, TPS650061
SLVS810B –JUNE 2009–REVISED AUGUST 2010 www.ti.com
The RSTSNS pin should be tied to VINDCDC if the reset functionality is not needed from this pin. This will cause
the reset to activate only when VINDCDC is rising from 0V or when VINDCDC has dropped below UVLO. The
RSTSNS pin should be connected to an external RC network to set the deglitch timing for triggering a reset when
VINDCDC is below the UVLO threshold. The reset threshold voltage is given by Equation 3:
(3)
The RST recovery timing is set by the capacitor on the TRST pin. A 2mA current is enabled when the reset
condition is met, charging the capacitor. The TRST voltage is monitored internally and the reset ends when the
voltage reaches 0.6V. The capacitor value to reset time can be computed with Equation 4:
(4)
The value t
RST
is the time from the end of condition that activated RST until RST returns to its Hi-Z state. The
TRST pin would be internally discharged to ground when the reset condition is true or after t
RST
.
Figure 29. RST Recovery Timing
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