Datasheet
SW
VINDCDC
FB_DCDC
L
C
O
R
DC2
Z
LOAD
EN_DCDC
MODE
V
REF(DCDC)
+
-
θ
JA
Diode
P
P
A
A
PGNDAGND
P
P
Oscillator
DISCHG
R
DC1
C
F
SwitchControl
( )
( )
DC1 DC2
DCDC FB_DCDC
DC2
DC1 DC2
DCDC
DC2
R + R
V = V x
R
R + R
V = 0.6V x
R
TPS65000, TPS65001, TPS650001
TPS650003, TPS650006, TPS650061
www.ti.com
SLVS810B –JUNE 2009–REVISED AUGUST 2010
DETAILED DESCRIPTION
Step-Down Converter
The step down converter is intended to allow maximum flexibility in the end equipment. The output voltage is
user selectable with a resistor network on the output. Figure 21 illustrates the necessary connections.
Figure 21. DCDC Block Diagram and Output Voltage Setting
The output voltage of the DCDC converter is set by Equation 1:
(1)
The combined resistance of R
DC1
and R
DC2
should be less than 1 MΩ.
Fixed output voltages and additional current limit options are also possible. Please contact Texas Instruments for
further information.
The step-down converter has two modes of operation to maximize efficiency at different load conditions. At
moderate to heavy load currents, the device operates in a fixed frequency pulse width modulation (PWM) mode
that results in small output ripple and high efficiency. Pulling the MODE pin to a DC high level will result in PWM
mode over the entire load range.
At light load currents, the device operates in a pulsed frequency modulation (PFM) mode to improve efficiency.
The transition to this mode occurs when the inductor current through the low-side FET becomes zero, indicating
discontinuous conduction. PFM mode also results in the output voltage increasing by 1% from its nominally set
value. This voltage positioning is intended to minimize the voltage undershoot of a load step from light to heavy
loads, as when a processor moves from sleep to active modes, and the voltage overshoot at load throw-off.
Figure 22 shows the voltage positioning behavior for a light to heavy load step.
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