Datasheet

1 2
1
R R
VIN _ OK VBIAS
R
æ ö
+
=
ç ÷
è ø
3 4
4
R R
VOUT VBIAS
R
æ ö
+
=
ç ÷
è ø
TPS62736
TPS62737
www.ti.com SLVSBO4B –OCTOBER 2012–REVISED JULY 2013
(3)
The VIN_OK setting is then given by Equation 4:
(4)
If it is preferred to disable the VIN_OK setting, the VIN_OK_SET pin can be tied to VIN as shown in Figure 4. To
set VOUT in this configuration, use Equation 3. To tighten the dc set point accuracy, use external resistors with
better than 1% resistor tolerance. Since output voltage ripple has a large effect on input line regulation and the
output load regulation, using a larger output capacitor will improve both line and load regulation.
Enable Controls
There are two enable pins implemented in the TPS6273X in order to maximize the flexibility of control for the
system. The EN1 pin is considered to be the chip enable. If EN1 is set to a 1 then the entire chip is placed into
ship mode. If EN1 is 0 then the chip is enabled. EN2 enables and disables the switching of the buck converter.
When EN2 is low, the internal circuitry remains ON and the VIN_OK indicator still functions. This can be used to
disable down-stream electronics in case of a low input supply condition. When EN2 is 1, the buck converter
operates normally.
Table 1. Enable Functionality Table
EN1 PIN EN2 PIN FUNCTIONAL STATE
0 0 Partial standby mode. Buck switching converter is off, but VIN_OK indication is on
0 1 Buck mode and VIN_OK enabled
1 x Full standby mode. Switching converter and VIN_OK indication is off (ship mode)
Startup Behavior
The TPS6273X has two startup responses: 1) from the ship-mode state (EN1 transitions from high to low), and
2) from the standby state (EN2 transitions from low to high). The first startup response out of the ship-mode
state has the longest time duration due to the internal circuitry being disabled. This response is shown in
Figure 38 for the TPS62736 and Figure 72 for the TPS62737. The startup time takes approximately 100ms due
to the internal Nano-Power management circuitry needing to complete the 64 ms sample and hold cycle.
Startup from the standby state is shown in Figure 39 for the TPS62736 and Figure 73 for the TPS62737. This
response is much faster due to the internal circuitry being pre-enabled. The startup time from this state is
entirely dependent on the size of the output capacitor. The larger the capacitor, the longer it will take to charge
during startup. The TPS6273X can startup into a pre-biased output voltage.
Steady State Operation and Cycle by Cycle Behavior
The steady state operation at full load is shown in Figure 31 for the TPS62736 and Figure 66 for TPS62737.
This plot highlights the inductor current waveform, the output voltage ripple, and the switching node. The output
voltage is maintained by charging and discharging the output capacitor at a primary duty cycle (major frequency)
which in turn dictates the output voltage ripple frequency. When VOUT is increasing in value, the output
capacitor is charged by the hysteretic buck controller. This is achieved by controlling the peak cycle-by-cycle
inductor current to I
LIM
. The cycle-by-cycle current is maintained by turning on and off the high side FET at a
secondary duty cycle (minor frequency). When VOUT reaches a peak value, all hysteretic control is disabled until
a minimum value is reached. The rate at which the converter stays off is dictated by the load and the size of the
output capacitor. At heavier output loads (larger output current), the time the converter is off is smaller when
compared to light load conditions. The light load condition is shown in Figure 32 for the TPS62736 and
Figure 65 for the TPS62737. Note that the converter is inactive for a longer period of time when compared to the
active time.
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