Datasheet

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R R R
VIN _ OK VBIAS
R
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R R R
VOUT VBIAS
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TPS62736
TPS62737
SLVSBO4B –OCTOBER 2012–REVISED JULY 2013 www.ti.com
DETAILED PRINCIPLE OF OPERATION
Step Down (Buck) Converter Operation
The buck regulator in the TPS6273X takes input power from VIN, steps it down and provides a regulated voltage
at the OUT pin. It employs pulse frequency modulation (PFM) control to regulate the voltage close to the desired
reference voltage. The reference voltage is set by the user programmed resistor divider. The current through the
inductor is controlled through internal current sense circuitry. The peak current in the inductor is controlled to
maintain high efficiency of the converter across a wide input current range. The TPS62736 converter delivers an
average output current of 50mA with a peak inductor current of 100 mA. The TPS62737 converter delivers an
average output current of 200 mA with a peak inductor current of 370 mA.The buck regulator is disabled when
the voltage on VIN reaches the UVLO condition. The UVLO level is continuously monitored. The buck regulator
continues to operate in pass (100% duty cycle) mode, passing the input voltage to the output, as long as VIN is
greater than UVLO and less than VIN minus I
OUT
times R
DS(on)
of the high-side FET (i.e., VIN - I
OUT
x R
DS(on)-HS
).
In order to save power from being dissipated through other IC’s on this supply rail while allowing for a faster
wake up time, the buck regulator can be enabled and disabled via the EN2 pin for systems that desire to
completely turn off the regulated output.
Nano-Power Management and Efficiency
The high efficiency of the TPS6273X is achieved via the proprietary Nano-Power management circuitry and
algorithm. This feature essentially samples and holds all references in order to reduce the average quiescent
current. That is, the internal circuitry is only active for a short period of time and then off for the remaining period
of time at the lowest feasible duty cycle. A portion of this feature can be observed in Figure 34 where the VRDIV
node is monitored. Here the VRDIV node provides a connection to the input (larger voltage level) and generates
the output reference (lower voltage level) for a short period of time. The divided down value of input voltage is
compared to VBIAS and the output voltage reference is sampled and held to get the VOUT_SET point. Since
this biases a resistor string, the current through these resistors is only active when the Nano-Power management
circuitry makes the connection—hence reducing the overall quiescent current due to the resistors. This process
repeats every 64 ms. Similarly,the VIN_OK level is monitored every 64ms, as shown in Figure 67.
The efficiency versus output current and versus input voltage are plotted for three different output voltages for
both the TPS62736 and TPS62737 in the Typical Characteristics section. All data points were captured by
averaging the overall input current. This must be done due to the periodic biasing scheme implemented via the
Nano-Power management circuitry. The input current efficiency data was gathered using a source meter set to
average over at least 25 samples and at the highest accuracy sampling rate. Each data point takes a long
period of time to gather in order to properly measure the resulting input current when calculating the efficiency.
Programming OUT Regulation Voltage and VIN_OK
To set the proper output regulation voltage and input voltage power good comparator, the external resistors must
be carefully selected. Figure 1 illustrates an application diagram which uses the minimal resistor count for setting
both VOUT and VIN_OK. Note that VBIAS is nominally 1.21V per the electrical specification table. Referring to
Figure 1, the OUT dc set point is given by:
(1)
The VIN_OK setting is given by:
(2)
The sum of the resistors is recommended to be no greater than 13 MΩ , that is, RSUM = R1 + R2 + R3 = 13
MΩ. Due to the sampling operation of the output resistors, lowering RSUM only increases quiescent current
slightly as can be seen in Figure 26. Higher resistors may result in poor output voltage regulation and/or input
voltage power good threshold accuracies due to noise pickup via the high impedance pins or reduction of
effective resistance due to parasitic resistances created from board assembly residue. See Layout
Considerations section for more details.
If it is preferred to separate the VOUT and VIN_OK resistor strings, two separate strings of resistors could be
used as shown in Figure 3. The OUT dc set point is then given by Equation 3:
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