Datasheet

J(MAX) A

D(MAX)

T - T

105 C - 85 C

P = = = 160mW

R 125 C/W

° °

YMSCC

LLLL

TPS62620, TPS62621

TPS62622, TPS62623

TPS62624, TPS62625

SLVS848C –JULY 2009– REVISED AUGUST 2011

www.ti.com

THERMAL INFORMATION

Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires

special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added

heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the

power-dissipation limits of a given component.

Three basic approaches for enhancing thermal performance are listed below:

• Improving the power dissipation capability of the PCB design

• Improving the thermal coupling of the component to the PCB

• Introducing airflow into the system

The maximum recommended junction temperature (T

) of the TPS6262x devices is 105°C. The thermal

resistance of the 6-pin CSP package (YFF-6) is R

θJA

= 125°C/W. Regulator operation is specified to a maximum

steady-state ambient temperature T

of 85°C. Therefore, the maximum power dissipation is about 160 mW.

(2)

PACKAGE SUMMARY

CHIP SCALE PACKAGE

(BOTTOM VIEW)

(TOP VIEW)

Code:

• YM — Year Month date Code

• S — Assembly site code

• CC— Chip code

• LLLL — Lot trace code

CHIP SCALE PACKAGE DIMENSIONS

The TPS6262x device is available in an 6-bump chip scale package (YFF, NanoFree™). The package

dimensions are given as:

• D = 1.30 ±0.03 mm

• E = 0.926 ±0.03 mm