Datasheet

V2
Time
V1
R1
R2
>
R3
R4
Voltage
Soft Start
100% Duty Cycle Low Dropout Operation
V min=V min+I maxxr max+R
I O O DS(on) L
()
(5)
Power Good
Undervoltage Lockout
TPS62510
www.ti.com ................................................................................................................................................................ SLVS651A – MAY 2006 – REVISED JULY 2009
If V2 needs to rise after V1, then R4 must be decreased as shown in Figure 21 .
Figure 21. V2 Comes Up After V1
The converter has an internal soft start circuit that limits the inrush current during start-up. The soft start is
realized by using a low current to control the output of the error amplifier during startup. The soft start time is
typically 750 µ s to ramp the output voltage to 95% of the final target value. There is a short delay of typically
120 µ s between the converter being enabled and switching activity actually starting. See the typical soft start
characteristic shown in Figure 14 .
The TPS62510 converter offers a low input to output voltage difference while maintaining operation with the use
of the 100% duty cycle mode. In this mode, the P-channel switch is constantly turned on. This is particularly
useful in battery-powered applications to achieve longest operation time by taking full advantage of the entire
battery voltage range. The minimum input voltage required to maintain dc regulation depends on the load current
and output voltage, and in Equation 5 .
with:
I
O
max = maximum load current (Note: ripple current in the inductor is zero under these conditions)
r
DS(on)
max = maximum P-channel switch r
DS(on)
RL = dc resistance of the inductor
V
O
min = nominal output voltage minus 2% tolerance limit
The power good output can be used for sequencing purposes, enabling a separate regulator once the output
voltage is reached, or to indicate that the output voltage is in regulation. When the device is disabled, the PG pin
is pulled low by the internal open-drain output transistor. Internally, the TPS62510 compares the feedback
voltage FB to the nominal reference voltage of typically 0.6 V. If the feedback voltage is more than 95% of this
value then the power good output goes high impedance. If the feedback voltage is less than 90% of the
reference voltage then PG pin is pulled low.
The undervoltage lockout circuit prevents the device from malfunctioning at low input voltages. It disables the
converter. The UVLO circuit monitors the AVIN pin, the falling threshold is set internally to 1.55 V with 150-mV
hysteresis. Note that when the dc-dc converter is running, there is an input current at the AVIN pin, which is up to
5 mA when in PWM mode. This current must be taken into consideration if an external RC filter is used at the
VCC pin to remove switching noise from the TPS62510 internal analog circuitry supply.
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