Datasheet

DVout + Vout
1 *
Vout
Vin
L ƒ
ǒ
1
8 Cout ƒ
) ESR
Ǔ
SW1
FB1
DEF_1
VIN2.5V – 6V
VIN
EN_1
EN_2
MODE/
DATA
TPS62420
GND
R11
R12
PowerPAD
R21
R22
SW2
ADJ2
C
10 F
IN
m
C
OUT2
C
33pF
ff2
L1
3.3 Hm
3.3 Hm
C
OUT2
L2
TPS62420-Q1
SLVSA56 –DECEMBER 2009 www.ti.com
(9)
Where the highest output voltage ripple occurs at the highest input voltage Vin.
At light load currents the converters operate in Power Save Mode and the output voltage ripple is dependent on
the output capacitor value. The output voltage ripple is set by the internal comparator delay and the external
capacitor. Higher output capacitors like 22μF values minimize the voltage ripple in PFM Mode and tighten DC
output accuracy in PFM Mode.
Input Capacitor Selection
Because of the nature of the buck converter having a pulsating input current, a low ESR input capacitor is
required for best input voltage filtering and minimizing the interference with other circuits caused by high input
voltage spikes. The converters need a ceramic input capacitor of 10μF. The input capacitor can be increased
without any limit for better input voltage filtering.
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well
as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and
short traces for the main current paths as indicated in bold in Figure 35.
The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output
capacitor.
Connect the GND Pin of the device to the PowerPAD of the PCB and use this Pad as a star point. For each
converter use a common Power GND node and a different node for the Signal GND to minimize the effects of
ground noise. Connect these ground nodes together to the PowerPAD (star point) underneath the IC. Keep the
common path to the GND PIN, which returns the small signal components and the high current of the output
capacitors as short as possible to avoid ground noise. The output voltage sense lines (FB 1, ADJ2, DEF_1)
should be connected right to the output capacitor and routed away from noisy components and traces (e.g., SW
line). If the EasyScale interface is operated with high transmission rates, the MODE/DATA trace must be routed
away from the ADJ2 line to avoid capacitive coupling into the ADJ2 pin. A GND guard ring between the
MODE/DATA pin and ADJ2 pin avoids potential noise coupling.
Figure 35. Layout Diagram
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