Datasheet

TPS62420-Q1
SLVSA56 –DECEMBER 2009 www.ti.com
The transmission of each byte needs to be closed with an End Of Stream condition for at least T
EOS
.
Addressable Registers
In TPS62420 two registers with a data content of 5 bits can be addressed to change the output voltage of both
converters. With 5 bit data content, 32 different values for each register are available. Table 1 shows the
addressable registers if DEF_1 pin acts as analog input with external resistors connected.
The available output voltages for converter 1 are shown in Table 3, for converter 2 in Table 4. To generate these
output voltages, a precise internal resistor divider network is used, which makes external resistors unnecessary
and results therefore in an higher output voltage accuracy and less board space.
The Interface is activated if at least one of the converters is enabled (EN1 or EN2 is high). After the Startup-time
t
Start
(170μs) the interface is ready for data reception.
Table 1. Addressable Registers for Adjustable Output Voltage Devices
REGISTER DESCRIPTION A1 A0 D4 D3 D2 D1 D0
REG_DEF_1_High Not available in TPS62420 adjustable version 0 1
REG_DEF_1_Low Converter 1 output voltage setting 0 0 TPS62420 see Table 3
REG_DEF_2 Converter 2 output voltage 1 0 TPS62420 see Table 4, connect ADJ2
pin directly to VOUT
2
Don’t use 1 1
Bit Decoding
The bit detection is based on a PWM scheme, where the criterion is the relation between t
LOW
and t
HIGH
. It can
be simplified to:
High Bit: t
High
> t
Low
, but with t
High
at least 2x t
Low
, see Figure 31
Low Bit: tLow> tHigh, but with tLow at least 2x tHigh, see Figure 31
The bit detection starts with a falling edge on the MODED/DATA pin and ends with the next falling edge.
Depending on the relation between t
Low
and t
High
a 0 or 1 is detected.
Acknowledge
The Acknowledge condition is only applied if:
• Acknowledge is requested by a set RFA bit
• The transmitted device address matches with the device address of the device
• 16 bits were received correctly
In this case, the device turns on the internal ACKN-MOSFET and pulls the MODE/DATA pin low for the time
tACKN, which is max. 520μs. The Acknowledge condition is valid after an internal delay time t
valACK
. This means
the internal ACKN-MOSFET is turned on after t
valACK
, when the last falling edge of the protocol was detected.
The master controller keeps the line low during this time.
The master device can detect the acknowledge condition with it’s input by releasing the MODE/DATA pin after
tvalACK and read back a 0.
In case of an invalid device address or not correctly received protocol, no acknowledge condition will be applied,
thus the internal MOSFET will not be turned on and the external pullup resistor pulls MODE/DATA pin high after
t
valACK
. The MODE/DATA pin can be used again after the acknowledge condition ends.
NOTE
The acknowledge condition may only be requested in case the master device has an
open drain output.
In case of a push pull output stage it is recommended to use a series resistor in the MODE/DATA line to limit the
current to 500μA in case of an accidentally requested acknowledge to protect the internal ACKN-MOSFET.
20 Submit Documentation Feedback Copyright © 2009, Texas Instruments Incorporated
Product Folder Link(s): TPS62420-Q1