Datasheet

TPS62410-Q1
SLVSAA8 –MARCH 2010 www.ti.com
EasyScale™: One Pin Serial Interface for Dynamic Output Voltage Adjustment
General
EasyScale is a simple but very flexible one pin interface to configure the output voltage of both DC/DC
converters. The interface is based on a master – slave structure, where the master is typically a µController or
Application processor. Figure 27 and Table 2 give an overview of the protocol. The protocol consists of a device
specific address byte and a data byte. The device specific address byte is fixed to 4E hex. The data byte
consists of five bit for information, two address bits and the RFA bit. RFA bit set to high indicates the Request
For Acknowledge condition. The Acknowledge condition is only applied if the protocol was received correctly.
The advantage of EasyScale compared to other one-pin interfaces is that its bit detection is, to a large extent,
independent from the bit transmission rate. It can automatically detect bit rates between 1.7kBit/sec and up to
160kBit/sec. Furthermore, the interface is shared with the Mode/Data Pin and requires therefore no additional
pin.
Protocol
All bits are transmitted MSB first and LSB last. Figure 28 shows the protocol without acknowledge request (bit
RFA = 0), Figure 29 with acknowledge (bit RFA = 1) request.
Prior to both bytes, device address byte and data byte, a start condition needs to be applied. For this, the
Mode/Data pin needs to be pulled high for at least t
Start
before the bit transmission starts with the falling edge. In
case the Mode/Data line was already at high level (forced PWM Mode selection) no start condition need be
applied prior the device address byte.
The transmission of each byte needs to be closed with an End Of Stream condition for at least T
EOS
.
Addressable Registers
In TPS62410 two registers with a data content of 5 bits can be addressed to change the output voltage of both
converters. With 5 bit data content, 32 different values for each register are available. Table 1 shows the
addressable registers if DEF_1 pin acts as analog input with external resistors connected.
The available output voltages for converter 1 are shown in Table 3, for converter 2 in Table 4. To generate these
output voltages, a precise internal resistor divider network is used, which makes external resistors unnecessary
and results therefore in an higher output voltage accuracy and less board space.
The Interface is activated if at least one of the converters is enabled (EN1 or EN2 is high). After the Startup-time
t
Start
(170µs) the interface is ready for data reception.
Table 1. Addressable Registers for Adjustable Output Voltage Devices
REGISTER DESCRIPTION A1 A0 D4 D3 D2 D1 D0
REG_DEF_1_High Not available in TPS62410 adjustable version 0 1
REG_DEF_1_Low Converter 1 output voltage setting 0 0 TPS62410 see Table 3
REG_DEF_2 Converter 2 output voltage 1 0 TPS62410 see Table 4, connect ADJ2
pin directly to VOUT
2
Don’t use 1 1
Bit Decoding
The bit detection is based on a PWM scheme, where the criterion is the relation between t
LOW
and t
HIGH
. It can
be simplified to:
High Bit: t
High
> t
Low
, but with t
High
at least 2x t
Low
, see Figure 30
Low Bit: t
Low
> t
High
, but with t
Low
at least 2x t
High
, see Figure 30
The bit detection starts with a falling edge on the MODE/DATA pin and ends with the next falling edge.
Depending on the relation between t
Low
and t
High
a 0 or 1 is detected.
Acknowledge
The Acknowledge condition is only applied if:
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