Datasheet

t
fDA
t
su;STA
Sr P
Sr
= MCS Current Source Pull-Up
= R
(P)
Resistor Pull-Up
SDAH
SCLH
Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.
See Note ASee Note A
t
hd;STA
t
rDA
t
hd;DAT
t
fCL
t
fCL1
t
fCL
t
su;DAT
t
LOW
t
HIGH
t
LOW
t
HIGH
t
rCL1
t
su;STO
t
f
HIGH
S
SDA
SCL
t
hd;STA
t
hd;DAT
t
r
t
LOW
t
su;DAT
t
f
t
hd;STA
t
hd;STA
t
su;STO
t
r
Sr P S
t
BUF
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com SLVSAU9C –MAY 2011–REVISED NOVEMBER 2012
I
2
C INTERFACE TIMING REQUIREMENTS
(1)(2)
(continued)
PARAMETER TEST CONDITIONS MIN MAX UNIT
Standard mode 20 + 0.1 C
B
1000 ns
Fast mode 20 + 0.1 C
B
300 ns
t
RDA
Rise time of SDA signal
High-speed mode, C
B
– 100 pF max 10 80 ns
High-speed mode, C
B
– 400 pF max 20 160 ns
Standard mode 20 + 0.1 C
B
300 ns
Fast mode 20 + 0.1 C
B
300 ns
t
FDA
Fall time of SDA signal
High-speed mode, C
B
– 100 pF max 10 80 ns
High-speed mode, C
B
– 400 pF max 20 160 ns
Standard mode 4 μs
t
SU
, t
STO
Setup time for STOP condition Fast mode 600 ns
High-speed mode 160 ns
C
B
Capacitive load for SDA and SCL 400 pF
I
2
C TIMING DIAGRAMS
Figure 1. Serial Interface Timing for F/S Mode
Figure 2. Serial Interface Timing for H/S Mode
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