Datasheet

TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9C –MAY 2011–REVISED NOVEMBER 2012 www.ti.com
Register 0x00h Description: SET0
The register settings apply by choosing SET0 ( VSEL1 = LOW, VSEL0 = LOW).
Table 13. TPS62360 Register 0x00h Description
REGISTER ADDRESS: 0x00h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET0
D7 MODE0 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 x Reserved for future use
Output voltage for SET0
D5 1
Default: (111111)
2
= 1.4V
D4 1 D5-D0 Output voltage
D3 1 00 0000 770 mV
00 0001 780 mV
OV0[5:0]
D2 1
00 0010 790 mV
. . . . . .
D1 1
11 1111 1400 mV
D0 LSB 1 V
OUT
= (xx xxxx)
2
× 10mV + 770 mV
Table 14. TPS62361B Register 0x00h Description
REGISTER ADDRESS: 0x00h Read/Write
BIT NAME DEFAULT DESCRIPTION
MSB Operation mode for SET0
D7 MODE0 0 0 = PFM / PWM mode operation
1 = Forced PWM mode operation
D6 0 Output voltage for SET0
Default: (0101110)
2
= 0.96V
D5 1
D4 0 D6-D0 Output voltage
D3 1 000 0000 500 mV
000 0001 510 mV
OV0[6:0]
D2 1
000 0010 520 mV
. . . . . .
D1 1
111 1111 1770 mV
D0 LSB 0 V
OUT
= (xxx xxxx)
2
× 10mV + 500 mV
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