Datasheet

TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9C –MAY 2011–REVISED NOVEMBER 2012 www.ti.com
THERMAL AND DEVICE LIFE TIME INFORMATION
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added
heat sinks and convection surfaces, and the presence of other heat-generating components affect the power-
dissipation limits of a given component.
Thermal performance can be enhanced by proper PCB layout. Wide power traces come with the ability to sink
dissipated heat. This can be improved further on multi layer PCB designs with vias to different layers.
Proper PCB layout with a focus on thermal performance results in a reduced junction-to-ambient thermal
resistance θ
JA
and thereby reduces the device junction temperature, T
J
.
The TI reliability requirement for the silicon chip's life time (100K Power-On-Hours at T
J
= 105°C) is affected by
the junction temperature and the continuously drawn current at the VIN pin and the SW pins. In order to be
consistent with the TI reliability requirement for the silicon chips (100000 Power-On-Hours at T
J
= 105°C), the
VIN pin current should not continuously exceed 1275mA and the SW pins current should not continuously
exceed 2550mA so as to prevent electromigration failure in the solder bump. Drawing 1150mA at VIN would, as
an example, be the case for typically I
OUT
= 2350mA, V
OUT
= 1.5V and V
IN
= 3.6V.
Exceeding the VIN pin / SW pins current rating might affect the device reliability. As an example, drawing current
peaks of I
OUT
= 3000mA with up to 10% of the application time over a base continuous output current of I
OUT
=
2000mA might reduce the Power-on-Hours to 90000 hours for conditions such as V
IN
= 2.7V, V
OUT
= 1.5V, T
J
=
105°C. In this example, exceeding T
J
= 105°C in combination with a higher peak output current duty cycle clearly
further affects the device life time.
For more details on how to use the thermal parameters, see the application notes: Thermal Characteristics
Application Note (SZZA017), and IC Package Thermal Metrics Application Note (SPRA953).
PCB LAYOUT
The PCB layout is an important step to maintain the high performance of the TPS6236x. Both the high current
and the fast switching nodes demand full attention to the PCB layout to save the robustness of the TPS6236x
through the PCB layout. Improper layout might show the symptoms of poor line or load regulation, ground and
output voltage shifts, stability issues, unsatisfying EMI behavior or worsened efficiency.
Signal Routing Strategy
The TPS6236x is a mixed signal IC. Depending on the function of a pin or trace, different board layout strategies
must be addressed to achieve a good design. Due to the nature of a switching converter, some signals are
sensitive to influence from other signals (aggressors). The sense lines, SENSE+ and SENSE-, are sensitive to
the aggressors, which are high bandwidth I/O pins (SCL and SDA) and the switch node (SW) and their
connected traces. Special care must be taken to avoid cross-talk between between them.
The following recommendations need to be followed:
• PGND, VIN and SW should be routed on thick layers. They must not surround inner signal layers which are
not able to withstand interference from noisy PGND, VIN and SW. They create a flux which is determined by
the switching frequency. The flux generated affects neighboring layers due to capacitive coupling across
layers.
• AGND, AVIN and VDD must be isolated from noisy signals.
• If crossing layers is required for PGND, VIN and SW, they must be dimensioned to support the high currents
to not cause high IR drops. In general, changing the layers frequently must be avoided.
• Signal traces, and especially the sense lines (SENSE+ and SENSE-), must be kept away from noisy traces/
signals. Avoid capacitive coupling with neighboring noisy layers by cutting away the overlapping areas close
to signal traces. Special care must be taken for the sense lines to avoid inductive / capacitive cross-talk from
aggressors, both from noisy lines as well as external inductors which generate magnetic fields.
• Care should be taken for a proper thermal layout. Wide traces, connecting through the layers with vias,
provides a proper thermal path to sink the heat energy created from the device and inductor.
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Product Folder Links: TPS62360 TPS62361B TPS62362 TPS62363