Datasheet

S HS-Master Code A Sr Register Address A
Data
A/A P
8
88
1
1
1
1
1
Slave Address R/W A
7
1
1
1
F/S Mode H/S Mode F/S Mode
Sr Slave Address
Sr Slave Address
H/S Mode continues
Data Transferred
(n x Bytes + Acknowledge)
From Device to Master
From Master to Device
A
A
S
Sr
P
=
=
=
=
=
Acknowledge (SDA low)
Acknowledge (SDA high)
START condition
REPEATED START condition
STOP condition
“0” Write
“1” Read
S Slave Address R/W A Register Address A
Sr
Slave Address R/W A
Data
A/A P
8
7
87
1
1
1
1
1
1
1
1
From Device to Master
From Master to Device
A
A
S
Sr
P
=
=
=
=
=
Acknowledge (SDA low)
Acknowledge (SDA high)
START condition
REPEATED START condition
STOP condition
1
S Register Address A
Data
A/A P
8
8
1
1
1
Slave Address R/W A
7
1
1
1
Slave Address
“0” Write
From Device to Master
From Master to Device
A
A
S
Sr
P
=
=
=
=
=
Acknowledge (SDA low)
Acknowledge (SDA high)
START condition
REPEATED START condition
STOP condition
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com SLVSAU9C –MAY 2011–REVISED NOVEMBER 2012
HS-Mode Protocol
When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices.
The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX.
This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS
master code, but all devices must recognize it and switch their internal setting to support 3.4 Mbps operation.
The master then generates a repeated start condition (a repeated start condition has the same timing as the start
condition). After this repeated start condition, the protocol is the same as F/S-mode, except that transmission
speeds up to 3.4Mbps are allowed. A stop condition ends the HS-mode and switches all the internal settings of
the slave devices to support the F/S-mode. Instead of using a stop condition, repeated start conditions should be
used to secure the bus in HS-mode.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
I
2
C UPDATE SEQUENCE
The TPS6236x requires a start condition, a valid I
2
C address, a register address byte, and a data byte for a
single update. After the receipt of each byte, the TPS6236x device acknowledges by pulling the SDA line low
during the high period of a single clock pulse. A valid I
2
C address selects the TPS6236x. The TPS6236x
performs an update on the falling edge of the acknowledge signal that follows the LSB byte.
Figure 45. Write Data Transfer Format in F/S-Mode
Figure 46. Read Data Transfer Format in F/S-Mode
Figure 47. Data Transfer Format in H/S-Mode
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Product Folder Links: TPS62360 TPS62361B TPS62362 TPS62363