Datasheet

START or
repeated START
Condition
Clock Line Held Low While
Interrupts are Serviced
S
Sr
or
SCL
1
2
ACK
7
9
8
1
2-8
9
ACK
Recognize START or
repeated START
Condition
Acknowledgment
Signal From Slave
SDA
Generate ACKNOWLEDGE
Signal
repeated START
or STOP
Condition
Sr
P
or
P
Sr
Recognize
repeated START
or STOP
Condition
Address
START condition
Clock Pulse for
Acknowledgment
Data Output
by Transmitter
S
SCL
1 2
8 9
Not Acknowledge
Acknowledge
Data Output
by Receiver
Data line stable;
data valid
Change of
data allowed
SDA
SCL
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9C –MAY 2011–REVISED NOVEMBER 2012 www.ti.com
The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W
on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires
the SDA line to be stable during the entire high period of the clock pulse (see Figure 42). All devices recognize
the address sent by the master and compare it to their internal fixed addresses. Only the slave device with a
matching address generates an acknowledge (see Figure 43) by pulling the SDA line low during the entire high
period of the ninth SCL cycle. Upon detecting this acknowledge, the master knows that communication link with a
slave has been established.
Figure 42. Bit Transfer on the Serial Interface
The master generates further SCL cycles to either transmit data to the slave (R/W bit 1) or receive data from the
slave (R/W bit 0). In either case, the receiver needs to acknowledge the data sent by the transmitter. So an
acknowledge signal can either be generated by the master or by the slave, depending on which one is the
receiver. 9-bit valid data sequences consisting of 8-bit data and 1-bit acknowledge can continue as long as
necessary.
To signal the end of the data transfer, the master generates a stop condition by pulling the SDA line from low to
high while the SCL line is high (see Figure 41). This releases the bus and stops the communication link with the
addressed slave. All I
2
C compatible devices must recognize the stop condition. Upon the receipt of a stop
condition, all devices know that the bus is released, and they wait for a start condition followed by a matching
address.
Attempting to read data from register addresses not listed in this section will result in 00h being read out.
Figure 43. Acknowledge on the I
2
C Bus
Figure 44. Bus Protocol
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