Datasheet

START condition
STOP condition
SDA
SCL
S
P
TPS62360, TPS62361B
TPS62362, TPS62363
www.ti.com SLVSAU9C –MAY 2011–REVISED NOVEMBER 2012
APPLICATION INFORMATION
I
2
C INTERFACE
Serial Interface Description
I
2
C is a 2-wire serial interface developed by Philips Semiconductor (see I
2
C-Bus Specification, Version 2.1,
January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the
bus is idle, both SDA and SCL lines are pulled high. All the I
2
C compatible devices connect to the I
2
C bus
through open drain I/O pins, SDA and SCL. A master device, usually a micro controller or a digital signal
processor, controls the bus. The master is responsible for generating the SCL signal and device addresses. The
master also generates specific conditions that indicate the START and STOP of data transfer. A slave device
receives and/or transmits data on the bus under control of the master device.
The TPS6236x device works as a slave and supports the following data transfer modes, as defined in the I
2
C-
Bus Specification:
• Standard mode (100 kbps)
• Fast mode (400 kbps)
• Fast mode plus (1Mbps)
• High-speed mode (3.4 Mbps)
The interface adds flexibility to the power supply solution, enabling most functions to be programmed to new
values depending on the instantaneous application requirements. Register contents remain intact as long as
VDD and AVIN are present in the specified range. Tripping the under voltage lockout of AVIN or VDD deletes the
registers and establishes the default values once the supply is present again.
The data transfer protocol for standard and fast modes is exactly the same; therefore, they are referred to as
F/S-mode in this document. The protocol for high-speed mode is different from F/S-mode, and it is referred to as
HS-mode. The TPS6236x device supports 7-bit addressing. 10-bit addressing and general call addressing are
not supported.
Table 6 shows the TPS6236x devices and their assigned I
2
C addresses.
Table 6. I
2
C Address
I
2
C ADDRESS
DEVICE OPTION
HEXADECIMAL
BINARY CODED
CODED
TPS62360 (0x60)
HEX
(110 0000)
2
TPS62361B (0x60)
HEX
(110 0000)
2
TPS62362 (0x60)
HEX
(110 0000)
2
TPS62363 (0x60)
HEX
(110 0000)
2
F/S-Mode Protocol
The master initiates data transfer by generating a start condition. The start condition is when a high-to-low
transition occurs on the SDA line while SCL is high, as shown in Figure 41. All I
2
C-compatible devices should
recognize a start condition.
Figure 41. START and STOP Conditions
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