Datasheet

Device Shutdown
Register Reset,
I C I/F Disabled
2
AVIN
VIN
VDD
VDD
Under Voltage?
AVIN
Under Voltage?
external low
ohmic connection
≥1
TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9C –MAY 2011–REVISED NOVEMBER 2012 www.ti.com
Die Temperature Monitoring and Over Temperature Protection
The TPS6236x offers two stages of die temperature monitoring and protection.
The Early Warning Monitoring Feature monitors the device temperature and provides the host an indication that
the die temperature is in the higher range. If the device's junction temperature, T
J
, exceeds 120°C typical, the
TJEW bit is set high. To avoid the thermal shutdown being triggered, the current drawn from the TPS6236x
should be reduced at this early stage.
The Over Temperature Protection feature disables the device if the temperature increases due to heavy load
and/or high ambient temperature. It monitors the device die temperature and, if required, triggers the device into
shutdown until the die temperature falls sufficiently.
If the junction temperature, T
J
, exceeds 150°C typical, the device goes into thermal shutdown. In this mode, the
power stage is turned off. During thermal shutdown, the I
2
C interface remains operable. All register values are
kept.
For the thermal shutdown, a hysteresis of 20°C typical is implemented allowing the device to cool after the
shutdown is triggered. Once the junction temperature T
J
cools down to 130°C typical, the device resumes
operation.
If a thermal shutdown has occurred, the TJTS bit is latched and remains a logic high as long as VDD and AVIN
are present and until the bit is reset by the host.
Input Under Voltage Protection
The input under voltage protection is implemented in order to prevent operation of the device for low input
voltage conditions. If the device is enabled, it prevents the device from switching if AVIN falls below the under
voltage lockout threshold. If the AVIN under voltage protection threshold is tripped, the device will go into under
voltage shutdown instantaneously, turning the power stage off and resetting all internal registers. The input under
voltage protection is also implemented on the VDD input. If the VDD under voltage protection threshold is
tripped, the device will reset all internal registers.
A under voltage lockout hysteresis of V
UVLO,HYST(AVIN)
at AVIN and V
UVLO,HYST(VDD)
at VDD is implemented.
The I
2
C compatible interface remains fully functional if AVIN and VDD are present. If the under voltage lockout of
AVIN or VDD is triggered during operation, all internal registers are reset to their default values. Figure 40 shows
the UVLO block diagram.
Figure 40. UVLO State Chart
By connecting VIN and AVIN to the same potential, VIN is included in the under voltage monitoring. If a low pass
input filter is applied at AVIN (not mandatory for the TPS6236x), the delay and shift in the voltage level can be
calculated by taking the typical quiescent current I
Q
at AVIN. As an example, for I
Q
and 10Ω series resistance,
this results in a minimal static shift of approx. 560µV.
VIN and AVIN must be connected to the same source for proper device operation.
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Product Folder Links: TPS62360 TPS62361B TPS62362 TPS62363