Datasheet

TPS62360, TPS62361B
TPS62362, TPS62363
SLVSAU9C –MAY 2011–REVISED NOVEMBER 2012 www.ti.com
The I
2
C interface is operable when VDD and AVIN are present, regardless of the state of the EN pin.
If the device is disabled by pulling the EN to a logic low, the output capacitor can actively be discharged. Per
default, this feature is disabled. Programming the EN_DISC bit to a logic high will discharge the output capacitor
via a typ. 300Ω path on the SENSE+ pin.
SOFT START
The device incorporates an internal soft start circuitry that controls the ramp up of the output voltage after
enabling the device. This circuitry eliminates inrush current to avoid excessive voltage drops of primary cells and
rechargeable batteries with high internal impedance.
During soft start, the output voltage is monotonically ramped up to the minimum programmable output voltage.
After reaching this threshold, the output voltage is further increased following the slope as programmed in the
ramp rate settings (see RAMP RATE CONTROLLING) until reaching the programmed output voltage. Once the
nominal voltage is reached, regular operation as described above will continue.
The device is able to start into a pre biased output capacitor as well.
PROGRAMMING THE OUTPUT
The TPS6236x devices offer four similar registers to program the output. Two dedicated hardware input pins,
VSEL0 and VSEL1, are implemented for choosing the active register. The logic state of VSEL0 and VSEL1
select the register whose settings are present at the output. The VSEL0 and VSEL1 pins must be terminated
unless the internal pull-down resistors are activated.
The registers have a certain initial default value (see Table 2) and can be readjusted via I
2
C during operation.
This allows a simple transition between several output options by triggering the dedicated input pins. At the same
time since the presets can be readjusted during operation, this offers highest flexibility.
Table 2. Output Presets
INPUT PINS DEFAULT OPERATION MODE DEFAULT OUTPUT VOLTAGE [V]
PRESET
I
2
C REGISTER
VSEL VSEL TPS62360, TPS62361B,
TPS62360 TPS62361B TPS62362 TPS62363
1 0 TPS62362, TPS62363
0 0 SET0 0x00h – see Table 13, Table 14, Power Save Mode 1.40 0.96 1.23 1.20
Table 15, Table 16
0 1 SET1 0x01h – see Table 17, Table 18, Power Save Mode 1.00 1.40 1.00 1.36
Table 19, Table 20
1 0 SET2 0x02h – see Table 21, Table 22, Power Save Mode 1.40 1.16 1.20 1.50
Table 23, Table 24
1 1 SET3 0x03h – see Table 25, Table 26, Power Save Mode 1.10 1.16 1.10 1.00
Table 27, Table 28
Via the I
2
C interface and/or the four preset options, the following output parameters can be changed:
• Output voltage from 0.77V to 1.4V (TPS62360/62) and 0.5V to 1.77V (TPS62361B/63) with 10mV granularity
• Mode of operation: Power Save Mode or forced PWM mode
The slope for transition between different output voltages (Ramp Rate) can be changed via I
2
C as well. The
slope applies for all presets globally. See RAMP RATE CONTROLLING for further details.
Since the output parameters can be changed by dedicated pins for selecting presets and by I
2
C, the following
use scenarios are feasible:
• Control the device via dedicated pins only, after programming the presets, to choose and change within the
programmed settings
• Program via I
2
C only. The dedicated input pins have fixed connections. Changes are conducted by changing
the preset values of the active register.
• Dedicated input pins and I
2
C mixed operation. The non active presets might be changed. The dedicated input
pins are used for the transition to the new output condition. Changes within an active preset via I
2
C are
feasible as well.
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Product Folder Links: TPS62360 TPS62361B TPS62362 TPS62363