Datasheet

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TPS6236x

PGND

AGND

LOAD

OUT

0.1µF

SENSE-

SENSE+

VIN

SCL

SDA

VSEL1

AVIN

VDD

2.5V .. 5.5V

0.47uH / 1µH

10µF

0.1µF

VSEL0

1mm

TPS62360, TPS62361B

TPS62362, TPS62363

www.ti.com

SLVSAU9C –MAY 2011–REVISED NOVEMBER 2012

3A Processor Supply with I

C Compatible Interface and Remote Sense

Check for Samples: TPS62360, TPS62361B, TPS62362, TPS62363

FEATURES

DESCRIPTION

The TPS6236x are a family of high-frequency

• 3A Peak Output Current

synchronous step down dc-dc converter optimized for

• Highest Efficiency:

battery-powered portable applications for a small

– Low R

DS,on

Switch and Active Rectifier

solution size. With an input voltage range of 2.5V to

5.5V, common battery technologies are supported.

– Power Save Mode for Light Loads

The device provides up to 3A peak load current,

• I

C High Speed Compatible Interface

operating at 2.5MHz typical switching frequency.

• Programmable Output Voltage for Digital

The devices convert to an output voltage range of

Voltage Scaling

0.77V to 1.4V (TPS62360/62) and 0.5V to 1.77V

– TPS62360/62: 0.77V to 1.4V, 10mV Steps

(TPS62361B/63), programmable via I

C interface in

– TPS62361B/63: 0.5V to 1.77V, 10mV Steps

10mV steps. Dedicated inputs allow fast voltage

transition to address processor performance

• Excellent DC/AC Output Voltage Regulation

operating points.

– Differential Load Sensing

The TPS6236x supports low-voltage DSPs and

– Precise DC Output Voltage Accuracy

processor cores in smart-phones and handheld

– DCS-Control™ Architecture for Fast and

computers including latest submicron processes.

Precise Transient Regulation

Dedicated hardware input pins allow simple

transitions to performance operating points and

• Multiple Robust Operation/Protection

retention modes of processors.

Features:

– Soft Start

The devices focus on a high output voltage accuracy.

The differential sensing and the DCS-Control™

– Programmable Slew Rate at Voltage

architecture achieve precise static and dynamic,

Transition

transient output voltage regulation.

– Over Temperature Protection

The TPS6236x devices offer high efficiency step

– Input Under Voltage Detection and Lockout

down conversion. The area of highest efficiency is

• Available in 16-Bump, 2mm x 2mm NanoFree™

extended towards low output currents to increase the

Package

efficiency while the processor is operating in retention

mode, as well as towards highest output currents

• Low External Device Count: < 25mm

Solution

increasing the battery on-time.

Size

The robust architecture and multiple safety features

APPLICATIONS

allow perfect system integration.

• Dynamic Voltage Scale Compliant Processors

The 2mm x 2mm package and the low number of

and DSPs, Memory

required external components lead to a tiny solution

size of less than 25mm

• SmartReflex™ Compliant Power Supply

• Cell Phones, Smart Phones, Feature Phones

• Tablets, Netbooks, Clamshells

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2DCS-Control, NanoFree, SmartReflex are trademarks of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (56 pages)

PAGE 1
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 3A Processor Supply with I2C Compatible Interface and Remote Sense Check for Samples: TPS62360, TPS62361B, TPS62362, TPS62363 FEATURES DESCRIPTION • • The TPS6236x are a family of high-frequency synchronous step down dc-dc converter optimized for battery-powered portable applications for a small solution size. With an input voltage range of 2.5V to 5.5V, common battery technologies are supported.
PAGE 2
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION (1) (2) DEVICE SPECIFIC FEATURES (1) PART NUMBER PACKAGE MARKING PACKAGE Output Voltage Range Output Voltage Presets TPS62360 (2) See PACKAGE SUMMARY Section CSP-16 VOUT = 0.
PAGE 3
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 THERMAL INFORMATION TPS6236x THERMAL METRIC (1) YZH UNITS 16 PINS Junction-to-ambient thermal resistance (2) θJA 94.8 (3) θJCtop Junction-to-case (top) thermal resistance θJB Junction-to-board thermal resistance (4) 60 ψJT Junction-to-top characterization parameter (5) 3.
PAGE 4
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted the specification applies for VIN = 3.6V over an operating ambient temp. –40°C ≤ TA ≤ 85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA = 25°C. PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 56 µA Forced PWM mode (Test Mode) 180 µA Input voltage falling, EN = High 2.
PAGE 5
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted the specification applies for VIN = 3.6V over an operating ambient temp. –40°C ≤ TA ≤ 85°C; Circuit of Parameter Measurement Information section (unless otherwise noted). Typical values are for TA = 25°C. PARAMETER TEST CONDITIONS Line regulation IOUT = 1A, forced PWM Load regulation VOUT = 1.
PAGE 6
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com I2C INTERFACE TIMING REQUIREMENTS (1) (2) PARAMETER f(SCL) TEST CONDITIONS SCL clock frequency Bus free time between a STOP and START condition tBUF MAX UNIT Standard mode MIN 100 kHz Fast mode 400 kHz High-speed mode (write operation), CB – 100 pF max 3.4 MHz High-speed mode (read operation), CB – 100 pF max 3.4 MHz High-speed mode (write operation), CB – 400 pF max 1.
PAGE 7
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 I2C INTERFACE TIMING REQUIREMENTS(1)(2) (continued) PARAMETER tRDA TEST CONDITIONS Rise time of SDA signal MIN MAX UNIT Standard mode 20 + 0.1 CB 1000 ns Fast mode 20 + 0.1 CB 300 ns 10 80 ns High-speed mode, CB – 100 pF max High-speed mode, CB – 400 pF max tFDA Fall time of SDA signal 20 160 ns Standard mode 20 + 0.1 CB 300 ns Fast mode 20 + 0.
PAGE 8
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com DEVICE INFORMATION PIN ASSIGNMENTS (TOP VIEW) (BOTTOM VIEW) AVIN AGND VSEL1 VIN A1 A2 A3 A4 SENSE+ EN SW SW B1 B2 B3 B4 PGND PGND SENSE- VSEL0 C1 C2 C3 C4 VDD SDA SCL PGND D1 D2 D3 D4 A4 A3 A2 A1 B4 B3 B2 B1 C4 C3 C2 C1 D4 D3 D2 D1 PIN FUNCTIONS PIN I/O DESCRIPTION NAME NO. AVIN A1 I Analog Supply Voltage Input. AGND A2 – Analog Ground Connection.
PAGE 9
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.
PAGE 10
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS Table of Graphs FIGURE vs. Output Current (Power Save and Forced PWM Mode) η Efficiency VOUT = 1.1V Figure 6 VOUT = 1.0V Figure 7 VOUT = 0.9V Figure 8 Figure 9 IOUT = 1000mA Figure 11 IOUT = 100mA Figure 12 IOUT = 10mA Figure 13 VOUT = 1.5V, TA = 25°C Figure 14 VOUT = 1.2V, TA = 25°C Figure 15 VOUT = 0.9V, TA = 25°C Figure 16 VOUT = 0.
PAGE 11
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs OUTPUT CURRENT VOUT = 1.4V 100 100 90 90 80 80 70 70 60 Efficiency (%) Efficiency (%) EFFICIENCY vs OUTPUT CURRENT VOUT = 1.5V TPS62361B VOUT = 1.5V TA = 25°C 50 40 30 10 0 1m 10m 100m Output Current (A) 1 TPS6236x VOUT = 1.4V TA = 25°C 50 40 30 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.
PAGE 12
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs OUTPUT CURRENT VOUT = 0.9V 100 100 90 90 80 80 70 70 60 Efficiency (%) Efficiency (%) EFFICIENCY vs OUTPUT CURRENT VOUT = 1.0V TPS6236x VOUT = 1.0V TA = 25°C 50 40 30 10 0 1m 10m 100m Output Current (A) 1 TPS6236x VOUT = 0.9V TA = 25°C 50 40 30 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.2V Auto PFM/PWM, VIN = 2.
PAGE 13
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 TYPICAL CHARACTERISTICS (continued) EFFICIENCY vs INPUT VOLTAGE IOUT = 100mA 100 100 90 90 80 80 70 70 60 60 Efficiency (%) Efficiency (%) EFFICIENCY vs INPUT VOLTAGE IOUT = 1A 50 40 30 0 2.5 40 30 20 10 50 Forced PWM, VOUT = 1.0V Forced PWM, VOUT = 1.1V Forced PWM, VOUT = 1.4V Auto PFM/PWM, VOUT = 1.0V Auto PFM/PWM, VOUT = 1.1V Auto PFM/PWM, VOUT = 1.4V 20 Auto PFM/PWM, VOUT = 1.
PAGE 14
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) DC OUTPUT VOLTAGE vs OUTPUT CURRENT VOUT = 1.2V DC OUTPUT VOLTAGE vs OUTPUT CURRENT VOUT = 0.9V 1.25 0.94 1.23 0.93 1.22 0.92 DC Output Voltage (V) DC Output Voltage (V) 1.24 0.95 TPS6236x VOUT = 1.2V TA = 25°C 1.21 1.20 1.19 1.18 1.16 1.15 1m 10m 100m Output Current (A) 1 0.91 0.90 0.89 0.88 Forced PWM, VIN = 2.8V Forced PWM, VIN = 3.6V Forced PWM, VIN = 4.
PAGE 15
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 TYPICAL CHARACTERISTICS (continued) STARTUP INTO NO LOAD VOUT = 1.5V TPS62361B RAMP[2:0] = 000 (32mV/μs) IOUT = 0A VIN = 3.6V VOUT = 1.5V STARTUP INTO LOAD VOUT = 0.5V TPS62361B RAMP[2:0] = 000 (32mV/μs) IOUT = 1A VIN = 3.6V VOUT = 0.5V VOUT 1V/Div VOUT 200mV/Div Inductor Current 500mA/Div Inductor Current 500mA/Div EN 2V/DIV EN 2V/DIV Time Base - 20μs/Div Time Base - 20μs/Div G019 G018 Figure 19.
PAGE 16
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) SWITCHING WAVE FORMS IOUT = 200mA TPS62361B IOUT = 200mA VIN = 3.6V VOUT = 1.2V SWITCHING WAVE FORMS IOUT = 1A TPS62361B IOUT = 1A VIN = 3.6V VOUT = 1.2V VOUT 10mV/Div w/ 1.2V Offset Inductor Current 200mA/Div w/ 200mA Offset VOUT 10mV/Div w/ 1.
PAGE 17
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 TYPICAL CHARACTERISTICS (continued) OUTPUT VOLTAGE RAMP CONTROL IOUT = 1A TPS62361B RAMP[2:0] = 000 (32mV/μs) LOAD TRANSIENT RESPONSE IOUT RANGE: 5mA to 200mA TPS62361B CLOAD = 22μF VOUT 1V/Div w/ 0.6V Offset VIN = 3.6V VOUT = 1.2V VOUT 20mV/Div w/ 1.2V Offset Inductor Current 500mA/Div IOUT = 1A VIN = 3.6V VOUT = 0.6V to 1.
PAGE 18
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com TYPICAL CHARACTERISTICS (continued) LOAD TRANSIENT RESPONSE IOUT RANGE: 1A to 3A LINE TRANSIENT RESPONSE VIN RANGE: 4.2V to 3.2V TPS62361B CIN = 100nF TPS62361B CLOAD = 22μF VIN = 3.6V VOUT = 1.2V VOUT = 1.2V CLOAD = 22μF IOUT = 300mA VIN 1V/Div w/ 4.2V Offset VOUT 50mV/Div w/ 1.2V Offset VOUT 20mV/Div w/ 1.
PAGE 19
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 TYPICAL CHARACTERISTICS (continued) QUIESCENT CURRENT vs INPUT VOLTAGE SWITCHING FREQUENCY vs OUTPUT CURRENT 300 1000 Switching Frequency (kHz) Quiescent Current (µA) 250 10000 TPS6236x MODE0 = 1 (Forced PWM) EN = HIGH 200 150 100 TPS6236x VOUT = 1.2V VIN = 3.6V 10 1 50 0 2.5 100 TA = −40°C, Forced PWM TA = 25°C, Forced PWM TA = 125°C, Forced PWM 3.0 3.5 4.0 4.5 Input Voltage (V) 5.
PAGE 20
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com PARAMETER MEASUREMENT INFORMATION TPS6236x VIN C2 C1 L VIN AVIN EN SW SW VDD SENSE+ SENSE- VOUT C4 SCL SDA VDD VSEL0 VSEL1 C3 PGND PGND AGND PGND Table 1. List of Components REFERENCE DESCRIPTION MANUFACTURER TPS6236x 3A Processor Supply with I2C Compatible Interface and Remote Sense Texas Instruments L 1 μH, 4 mm x 4 mm x 2.1 mm Coilcraft (XFL4020-102ME1.0) C2, C4 10 μF, Ceramic, 6.
PAGE 21
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 DETAILED DESCRIPTION The TPS6236x are a family of high-frequency synchronous step down dc-dc converter optimized for batterypowered portable applications. With an input voltage range of 2.5V to 5.5V, common battery technologies are supported. The device provides up to 3A peak load current, operating at 2.5MHz typical switching frequency. The devices convert to an output voltage range of 0.77V to 1.
PAGE 22
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com The I2C interface is operable when VDD and AVIN are present, regardless of the state of the EN pin. If the device is disabled by pulling the EN to a logic low, the output capacitor can actively be discharged. Per default, this feature is disabled. Programming the EN_DISC bit to a logic high will discharge the output capacitor via a typ. 300Ω path on the SENSE+ pin.
PAGE 23
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 DYNAMIC VOLTAGE SCALING The output voltage can be adjusted dynamically. Each of the four output registers can be programmed individually by setting OV[5:0] (TPS62360/62) and OV[6:0] (TPS62361B/63) respectively in the SET0, SET1, SET2 and SET3 registers. Table 3.
PAGE 24
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com The TPS6236x is optimized for low output voltage ripple. Therefore, the peak inductor current in PFM mode is kept small and can be calculated as follows: IL,PFM,peak = t ON ´ (VIN - VOUT ) L (2) And: t ON = VOUT ´ 350ns + 20ns VIN (3) With: VIN = Input Voltage VOUT = Output Voltage tON = On-time of the High Side FET, from Equation 3 L = Inductor value The TPS6236x offers a forced PWM mode as well.
PAGE 25
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 If the RAMP_PFM bit is not set in Power Save Mode, the slope can be less at low output currents since the device does not actively source energy back from the output capacitor to the input or it might be sharper at high output currents since the output capacitor is discharged quickly.
PAGE 26
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com Die Temperature Monitoring and Over Temperature Protection The TPS6236x offers two stages of die temperature monitoring and protection. The Early Warning Monitoring Feature monitors the device temperature and provides the host an indication that the die temperature is in the higher range. If the device's junction temperature, TJ, exceeds 120°C typical, the TJEW bit is set high.
PAGE 27
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 APPLICATION INFORMATION I2C INTERFACE Serial Interface Description I2C is a 2-wire serial interface developed by Philips Semiconductor (see I2C-Bus Specification, Version 2.1, January 2000). The bus consists of a data line (SDA) and a clock line (SCL) with pull-up structures. When the bus is idle, both SDA and SCL lines are pulled high.
PAGE 28
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com The master then generates the SCL pulses, and transmits the 7-bit address and the read/write direction bit R/W on the SDA line. During all transmissions, the master ensures that data is valid. A valid data condition requires the SDA line to be stable during the entire high period of the clock pulse (see Figure 42).
PAGE 29
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 HS-Mode Protocol When the bus is idle, both SDA and SCL lines are pulled high by the pull-up devices. The master generates a start condition followed by a valid serial byte containing HS master code 00001XXX. This transmission is made in F/S-mode at no more than 400 Kbps. No device is allowed to acknowledge the HS master code, but all devices must recognize it and switch their internal setting to support 3.
PAGE 30
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com Slave Address Byte MSB X X X X X X A1 LSB A0 The slave address byte is the first byte received following the START condition from the master device. Register Address Byte MSB 0 0 0 0 0 D2 D1 LSB D0 Following the successful acknowledgment of the slave address, the bus master will send a byte to the TPS6236x, which will contain the address of the register to be accessed.
PAGE 31
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 Table 7. List of Recommended Capacitors CAPACITANCE [µF] TYPE DIMENSIONS L x W x H [mm3] MANUFACTURER 10 GRM188R60J106M 0603: 1.6 x 0.8 x 0.8 Murata 10 CL10A106MQ8NRNC 0603: 1.6 x 0.8 x 0.8 Samsung 22 GRM188R60G226M 0603: 1.6 x 0.8 x 0.8 Murata 22 CL10A106MQ8NRNC 0603: 1.6 x 0.8 x 0.
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TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 IL,MAX = IOUT,MAX + www.ti.com ΔIL 2 (6) With: ΔIL = Inductor ripple current (see Equation 5) IOUT,MAX = Maximum output current Since the inductance can be decreased by saturation effects and temperature impact, the inductor needs to be chosen to have an effective inductance of at least 0.3µH under temperature and saturation effects. Table 8 shows a list of inductors that have been used with the TPS6236x.
PAGE 33
TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 TPS6236x L SW SW COUT LOAD SENSE+ CLOAD SENSE- PGND PGND PGND Figure 50. L, COUT and CLOAD Forming the Output Filter Depending on the chosen inductor value, a certain minimum output capacitor COUT must be present. Also depending on the chosen inductor value, a maximum output and buffer capacitor configuration (COUT + CLOAD) must not be exceeded.
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TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com THERMAL AND DEVICE LIFE TIME INFORMATION Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires special attention to power dissipation. Many system-dependent issues such as thermal coupling, airflow, added heat sinks and convection surfaces, and the presence of other heat-generating components affect the powerdissipation limits of a given component.
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TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 External Components Placement The input capacitor at VIN must be placed closest to the IC for proper operation. The decoupling caps at AVIN and VDD reduce noise impacts and should be placed as close to the IC as possible. The output filter, consisting of COUT and L, converts the switching signal at SW to the noiseless output voltage.
PAGE 36
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com REGISTER SETTINGS Overview Table 9.
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TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 Table 12.
PAGE 38
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com Register 0x00h Description: SET0 The register settings apply by choosing SET0 ( VSEL1 = LOW, VSEL0 = LOW). Table 13. TPS62360 Register 0x00h Description REGISTER ADDRESS: 0x00h Read/Write BIT NAME D7 MODE0 DEFAULT MSB DESCRIPTION 0 Operation mode for SET0 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 1 Output voltage for SET0 Default: (111111)2 = 1.
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TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 Table 15. TPS62362 Register 0x00h Description REGISTER ADDRESS: 0x00h Read/Write BIT NAME D7 MODE0 DEFAULT MSB DESCRIPTION 0 Operation mode for SET0 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 1 Output voltage for SET0 Default: (101110)2 = 1.23V D4 0 D5-D0 Output voltage D3 1 00 0000 770 mV 00 0001 780 mV 00 0010 790 mV ... ...
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TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com Register 0x01h Description: SET1 The register settings apply by choosing SET1 ( VSEL1 = LOW, VSEL0 = HIGH). Table 17. TPS62360 Register 0x01h Description REGISTER ADDRESS: 0x01h Read/Write BIT NAME D7 MODE1 DEFAULT MSB DESCRIPTION 0 Operation mode for SET1 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 0 Output voltage for SET1 Default: (010111)2 = 1.
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TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 Table 19. TPS62362 Register 0x01h Description REGISTER ADDRESS: 0x01h Read/Write BIT NAME D7 MODE1 DEFAULT MSB DESCRIPTION 0 Operation mode for SET1 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 0 Output voltage for SET1 Default: (010111)2 = 1.0V D4 1 D5-D0 Output voltage D3 0 00 0000 770 mV 00 0001 780 mV 00 0010 790 mV ... ...
PAGE 42
TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com Register 0x02h Description: SET2 The register settings apply by choosing SET2 ( VSEL1 = HIGH, VSEL0 = LOW). Table 21. TPS62360 Register 0x02h Description REGISTER ADDRESS: 0x02h Read/Write BIT NAME D7 MODE2 DEFAULT MSB DESCRIPTION 0 Operation mode for SET2 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 1 Output voltage for SET2 Default: (111111)2 = 1.
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TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 Table 23. TPS62362 Register 0x02h Description REGISTER ADDRESS: 0x02h Read/Write BIT NAME D7 MODE2 DEFAULT MSB DESCRIPTION 0 Operation mode for SET2 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 1 Output voltage for SET2 Default: (101011)2 = 1.2V D4 0 D5-D0 Output voltage D3 1 00 0000 770 mV 00 0001 780 mV 00 0010 790 mV ... ...
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TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com Register 0x03h Description: SET3 The register settings apply by choosing SET3 ( VSEL1 = HIGH, VSEL0 = HIGH). Table 25. TPS62360 Register 0x03h Description REGISTER ADDRESS: 0x03h Read/Write BIT NAME D7 MODE3 DEFAULT MSB DESCRIPTION 0 Operation mode for SET3 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 1 Output voltage for SET3 Default: (100001)2 = 1.
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TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 Table 27. TPS62362 Register 0x03h Description REGISTER ADDRESS: 0x03h Read/Write BIT NAME D7 MODE3 DEFAULT MSB DESCRIPTION 0 Operation mode for SET3 0 = PFM / PWM mode operation 1 = Forced PWM mode operation D6 x Reserved for future use D5 1 Output voltage for SET3 Default: (100001)2 = 1.1V D4 0 D5-D0 Output voltage D3 0 00 0000 770 mV 00 0001 780 mV 00 0010 790 mV ... ...
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TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com Register 0x04h Description: Ctrl Table 29.
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TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 Register 0x06h Description: RmpCtrl Table 31. TPS6236x Register 0x06h Description REGISTER ADDRESS: 0x06h Read/Write BIT NAME DEFAULT MSB D7 D6 DESCRIPTION Output voltage ramp timing 0 0 RMP[2:0] D7-D5 Slope 000 32 mV / µs 001 16 mV / µs 010 8 mV / µs ... ... 110 0.5 mV / µs 111 0.
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TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com Register 0x08h, 0x09h Description Chip_ID: Table 33. TPS6236x Register 0x08h and 0x09h Description REGISTER ADDRESS: 0x08h, 0x09 Read BIT D7 NAME DEFAULT MSB D6 0 D5 0 D4 0 D3 x D2 x D1 x D0 x LSB 48 DESCRIPTION 1 Vendor ID D3-D2 Part number ID 00 TPS62360 01 TPS62361B 10 TPS62362 11 TPS62363 D1-D0 Chip revision ID 00 Rev. 1 01 Rev. 2 10 Rev. 3 11 Rev.
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TPS62360, TPS62361B TPS62362, TPS62363 www.ti.com SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 PACKAGE SUMMARY CHIP SCALE PACKAGE (TOP VIEW) Code: TIYMLLLLS XXXXXXXXX E • TI — Texas Instruments • YM — Year Month date code • LLLL — Lot trace code • S — Assembly site code • XXXXXXXX — Part number • TPS62360 = TPS62360 • TPB62361 = TPS62361B • TPS62362 = TPS62362 • TPS62363 = TPS62363 A1 D Figure 53.
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TPS62360, TPS62361B TPS62362, TPS62363 SLVSAU9C – MAY 2011 – REVISED NOVEMBER 2012 www.ti.com REVISION HISTORY Changes from Revision B (March 2012) to Revision C Page • Changed solution size of approximately 27.5 mm2 to 25 mm2 ............................................................................................. 1 • Changed application schematic ............................................................................................................................................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 1-Feb-2014 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) TPS62360YZHR DSBGA YZH 16 3000 180.0 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 2.18 2.18 0.81 4.0 8.0 Q1 TPS62360YZHT DSBGA YZH 16 250 180.0 8.4 2.18 2.18 0.81 4.0 8.0 Q1 TPS62361BYZHR DSBGA YZH 16 3000 180.0 8.4 2.18 2.18 0.81 4.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 1-Feb-2014 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TPS62360YZHR DSBGA YZH 16 3000 182.0 182.0 17.0 TPS62360YZHT DSBGA YZH 16 250 182.0 182.0 17.0 TPS62361BYZHR DSBGA YZH 16 3000 182.0 182.0 17.0 TPS62361BYZHT DSBGA YZH 16 250 182.0 182.0 17.0 TPS62362YZHR DSBGA YZH 16 3000 182.0 182.0 17.0 TPS62362YZHT DSBGA YZH 16 250 182.0 182.0 17.
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D: Max = 2.086 mm, Min =2.026 mm E: Max = 2.086 mm, Min =2.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.