Datasheet

I
2
C TIMING DIAGRAMS
t
f
t
LOW
t
r
t
hd;STA
t
hd;DAT
t
su;DAT
t
f
HIGH
t
su;STA
S Sr P S
t
hd;STA
t
r
t
BUF
t
su;STO
SDA
SCL
Sr PSr
t
fDA
t
rDA
t
hd;DAT
t
su;STA
t
hd;STA
t
su;DAT
t
su;STO
t
rCL1
t
fCL
t
HIGH
t
LOW
t
LOW
t
HIGH
t
rCL
t
rCL1
= MCS Current Source Pull-Up
= R
(P)
Resistor Pull-Up
SDAH
SCLH
Note A: First rising edge of the SCLH signal after Sr and after each acknowledge bit.
See Note ASee Note A
TPS62350, TPS62351
TPS62352, TPS62353
TPS62354, TPS62355, TPS62356
SLVS540E – MAY 2006 – REVISED APRIL 2008 .............................................................................................................................................................. www.ti.com
Figure 1. Serial Interface Timing Diagram for F/S-Mode
Figure 2. Serial Interface Timing Diagram for HS-Mode
8 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS62350, TPS62351 TPS62352, TPS62353 TPS62354, TPS62355, TPS62356