Datasheet
Layout Considerations
PVIN
AVIN
SW
TPS6235x
L1
C1
V
O
PGND
C2
V
I
AGND
FB
SYNC
EN
VSEL
SDA
SCL
Thermal Information
P MAX=
D
T
J A
MAX- T
=
R
qJA
125 C-85 C
o o
89 C/W
o
=450mW
(4)
TPS62350, TPS62351
TPS62352, TPS62353
TPS62354, TPS62355, TPS62356
SLVS540E – MAY 2006 – REVISED APRIL 2008 ..............................................................................................................................................................
www.ti.com
As for all switching power supplies, the layout is an important step in the design. High-speed operation of the
TPS6235x device demands careful attention to PCB layout. Care must be taken in board layout to get the
specified performance. If the layout is not carefully done, the regulator could show poor line and/or load
regulation, stability issues as well as EMI problems. It is critical to provide a low inductance, impedance ground
path. Therefore, use wide and short traces for the main current paths as indicated in bold on Figure 53 .
The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output
capacitor. Use a common ground node for power ground and a different one for control ground (AGND) to
minimize the effects of ground noise. Connect these ground nodes together (star point) underneath the IC and
make sure that small signal components returning to the AGND pin do not share the high current path of C1 and
C2.
The output voltage sense line (FB) should be connected right to the output capacitor and routed away from noisy
components and traces (e.g., SW line). Its trace should be minimized and shielded by a guard-ring connected to
the reference ground.
Figure 53. Layout Diagram
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the
power-dissipation limits of a given component.
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
The maximum recommended junction temperature (T
J
) of the TPS6235x device is 125 ° C. The thermal resistance
of the 12-pin CSP package (YZG) is R
θ JA
= 89 ° C/W. Specified regulator operation is assured to a maximum
ambient temperature T
A
of 85 ° C. Therefore, the maximum power dissipation is about 450 mW. More power can
be dissipated if the maximum ambient temperature of the application is lower or if the PowerPAD™ package
(DRC) is used.
36 Submit Documentation Feedback Copyright © 2006 – 2008, Texas Instruments Incorporated
Product Folder Link(s): TPS62350, TPS62351 TPS62352, TPS62353 TPS62354, TPS62355, TPS62356