Datasheet

CONTROL2 REGISTER (READ/WRITE)
Memorylocation:03
Resetstate:00000111
DEFSLEW
7 6 5 4 3 2 1 0
MSB LSB
DEFSLEWdefinestheoutputvoltageramprate
PLL_MULT
OUTPUT_DISCHARGE
GO
000:0.15mV/ sm
001:0.3mV/ sm
010:0.6mV/ sm
011:1.2mV/ sm
100:2.4mV/ sm
101:4.8mV/ sm
110:9.6mV/ sm
111:Immediate(default)
PLL_MULT definesthesynchronizationclockmultiplierratio
00:x1-f
(SYNC)
=3MHz±12%(default)
01:x2-f
(SYNC)
=1.5MHz±12%
10:x3-f
(SYNC)
=1MHz±12%
11:x4-f
(SYNC)
=750kHz±12%
0: Thedc/dcoutputcapacitorisnotactivelydischarged
whentheconverterisdisabled(default).
1: Thedc/dcoutputcapacitorisactivelydischargedwhenthe
converterisdisabled.
ThisbitisonlyvalidwhenHW_nSW=0
1: Theoutputvoltageischangedwiththerampratedefined
inDEFSLEW.
0:Nochangeintheoutputvoltage (default).
PWROK(READONLY)
0:Indicatesthattheoutputvoltageisbelowitstargetregulation
voltage. Thisbitiszeroiftheconverterisdisabled.
1:Indicatesthattheoutputvoltageiswithinitsnominalrange
TPS62350, TPS62351
TPS62352, TPS62353
TPS62354, TPS62355, TPS62356
www.ti.com .............................................................................................................................................................. SLVS540E – MAY 2006 – REVISED APRIL 2008
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Product Folder Link(s): TPS62350, TPS62351 TPS62352, TPS62353 TPS62354, TPS62355, TPS62356