Datasheet

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THERMAL INFORMATION
P
D(MAX)
+
T
J(MAX)
* T
A
R
qJA
+
125°C * 85°C
250°CńW
+ 160 mW
(6)
CHIP SCALE PACKAGE DIMENSIONS
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
Implementation of integrated circuits in low-profile and fine-pitch surface-mount packages typically requires
special attention to power dissipation. Many system-dependant issues such as thermal coupling, airflow, added
heat sinks, and convection surfaces, and the presence of other heat-generating components, affect the
power-dissipation limits of a given component
Three basic approaches for enhancing thermal performance are listed below:
• Improving the power dissipation capability of the PCB design
• Improving the thermal coupling of the component to the PCB
• Introducing airflow in the system
The maximum recommended junction temperature (T
J
) of the TPS6230x, TPS6231x, and TPS6232x devices is
125 ° C. The thermal resistance of the 8-pin CSP package (YZD, YZ and YED) is R
θ JA
= 250 ° C/W. Specified
regulator operation is specified to a maximum ambient temperature T
A
of 85 ° C. Therefore, the maximum power
dissipation is about 160 mW. More power can be dissipated if the maximum ambient temperature of the
application is lower, or if the PowerPAD™ package (DRC) is used.
The TPS6230x, TPS6231x, and TPS6232x are also available in an 8-bump chip scale package (YZD, YZ
NanoFree™ and YED, NanoStar™). The package dimensions are given as:
• D = 1.970 ± 0.05 mm
• E = 0.970 ± 0.05 mm
22 Submit Documentation Feedback Copyright © 2004 – 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321