Datasheet

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LAYOUT CONSIDERATIONS
AVIN
VIN
SW
TPS62300
L1
ADJ
PGND
AGND
VOUT
R1
R2
EN
MODE/SYNC
FB
1
2
3
8
7
10
6
4
5
9
V
I
C1
C2
V
O
GND
MODE / SYNC
V
O
sense signal
EN
V
I
GND
V
O
TPS62300, TPS62301, TPS62302
TPS62303, TPS62304, TPS62305,
TPS62311, TPS62313, TPS62315, TPS62320, TPS62321
SLVS528E – JULY 2004 – REVISED NOVEMBER 2007
As for all switching power supplies, the layout is an important step in the design. High-speed operation of the
TPS6230x, TPS6231x, and TPS6232x devices demand careful attention to PCB layout. Care must be taken in
board layout to get the specified performance. If the layout is not carefully done, the regulator could show poor
line and/or load regulation, stability issues as well as EMI problems. It is critical to provide a low inductance,
impedance ground path. Therefore, use wide and short traces for the main current paths as indicated in bold on
Figure 34 .
The input capacitor should be placed as close as possible to the IC pins as well as the inductor and output
capacitor. Use a common ground node for power ground and a different one for control ground (AGND) to
minimize the effects of ground noise. Connect these ground nodes together (star point) underneath the IC and
make sure that small signal components returning to the AGND pin do not share the high current path of C1 and
C2.
The output voltage sense line (VOUT) should be connected right to the output capacitor and routed away from
noisy components and traces (e.g., SW line). Its trace should be minimized and shielded by a guard-ring
connected to the reference ground. The voltage setting resistive divider should be placed as close as possible to
the AGND pin of the IC.
Figure 34. Layout Diagram
Figure 36. Suggested QFN Layout (Bottom)
Figure 35. Suggested QFN Layout (Top)
Copyright © 2004 – 2007, Texas Instruments Incorporated Submit Documentation Feedback 21
Product Folder Link(s): TPS62300, TPS62301, TPS62302 TPS62303, TPS62304, TPS62305, TPS62311, TPS62313,
TPS62315, TPS62320, TPS62321