Datasheet
Zero-Pole
Amp.
Integrator
Error Amplifier
+1% Voltagepositioning
PWM
Comp.
VREF
Control
Stage
GateDriver
Anti-
Shoot-Through
Current-
LimitComparator
Current-
LimitComparator
VREF +1%
FB
FB
V
IN
GND
MODE
2.25-MHz
Oscillator
SW1
EN
V
IN
Softstart
VOUT RAMP
CONTROL
Thermal
Shutdown
.6
Reference
0 VVREF
Undervoltage
Lockout 1.8 V
Limit
HighSide
Limit
LowSide
Sawtooth
Generator
Int. Resistor
Network
FB
RI3
RI 1
RI..N
MODE
Onlyin 2x2SON
GND
PFMComparator
DRV PACKAGE
(TOP VIEW)
MODE
FB
GNDSW
EN
VIN
1
2
3
6
5
4
Exposed
Thermal
Pad
TPS62260-Q1, TPS62261-Q1
TPS62262-Q1, TPS62263-Q1
SLVSA16C –AUGUST 2009–REVISED JULY 2012
www.ti.com
PIN ASSIGNMENTS
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NAME NO.
This is the switch pin and is connected to the internal MOSFET switches. Connect the external inductor
SW 1 OUT
between this terminal and the output capacitor.
This pin is only available at SON package option. MODE pin = high forces the device to operate in fixed
MODE 2 I frequency PWM mode. MODE pin = low enables the Power Save Mode with automatic transition from
PFM mode to fixed frequency PWM mode.
Feedback for the internal regulation loop. Connect the external resistor divider to this pin. In case of
FB 3 I
fixed output voltage option, connect this pin directly to the output capacitor.
This is the enable pin of the device. Pulling this pin to low forces the device into shutdown mode. Pulling
EN 4 I
this pin to high enables the device. This pin must be terminated.
V
IN
5 PWR Power supply
GND 6 PWR Ground
FUNCTIONAL BLOCK DIAGRAM
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Product Folder Link(s): TPS62260-Q1 TPS62261-Q1 TPS62262-Q1 TPS62263-Q1