Datasheet

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PIN ASSIGNMENTS
V
IN
GND
EN
SW
FB
1
2
3
5
4
DDCPACKAGE
(TOP VIEW)
DRV PACKAGE
(TOPVIEW)
MODE
FB
GNDSW
EN
VIN
1
2
3
6
5
4
r
P
o
we
PAD
Zero-Pole
AMP.
Integrator
Error Amp .
PFMComparator
PWM
Comp.
VREF
Control
Stage
GateDriver
Anti-
Shoot-Through
Current
LimitComparator
Current
LimitComparator
VREF
FB
FB
VIN
GND
MODE
2.25 MHz
Oscillator
SW1
EN
VIN
Softstart
VOUT RAMP
CONTROL
Thermal
Shutdown
Reference
0.6VVREF
Undervoltage
Lockout 1.8V
Limit
HighSide
Limit
LowSide
Sawtooth
Generator
Int. Resistor
Network
FB
RI3
RI 1
RI..N
Mode
Onlyin 2x2SON
GND
TPS62240 , TPS62242 , TPS62243
SLVS762B – JUNE 2007 – REVISED SEPTEMBER 2007
TERMINAL FUNCTIONS
TERMINAL
I/O DESCRIPTION
NO. NO.
NAME
(SON) TSTO23-5
V
IN
5 1 PWR V
IN
power supply pin.
GND 6 2 PWR GND supply pin
This is the enable pin of the device. Pulling this pin to low forces the device into shutdown
EN 4 3 I
mode. Pulling this pin to high enables the device. This pin must be terminated.
This is the switch pin and is connected to the internal MOSFET switches. Connect the inductor
SW 1 5 OUT
to this terminal.
Feedback Pin for the internal regulation loop. Connect the external resistor divider to this pin.
FB 3 4 I
In case of fixed output voltage option, connect this pin directly to the output capacitor.
This pin is only available at SON package option. MODE pin = high forces the device to
MODE 2 I operate in fixed frequency PWM mode. MODE pin = low enables the Power Save Mode with
automatic transition from PFM mode to fixed frequency PWM mode.
FUNCTIONAL BLOCK DIAGRAM
4 Submit Documentation Feedback Copyright © 2007, Texas Instruments Incorporated
Product Folder Link(s): TPS62240 TPS62242 TPS62243