Datasheet

V
IN
GND
V
OUT
C
1
C2
L1
Totalarea
islessthan
12mm²
TPS62230, TPS62231, TPS62232, TPS62233, TPS62234, TPS62235, TPS62236
TPS62237, TPS62238, TPS62239, TPS622310, TPS622311, TPS622312
TPS622313, TPS622314, TPS622315, TPS622316, TPS622317, TPS622318
www.ti.com SLVS941E –APRIL 2009–REVISED DECEMBER 2010
CHECKING LOOP STABILITY
The first step of circuit and stability evaluation is to look from a steady-state perspective at the following signals:
• Switching node, SW
• Inductor current, I
L
• Output ripple voltage, V
OUT(AC)
These are the basic signals that need to be measured when evaluating a switching converter. When the
switching waveform shows large duty cycle jitter or the output voltage or inductor current shows oscillations, the
regulation loop may be unstable. This is often a result of board layout and/or L-C combination.
As a next step in the evaluation of the regulation loop, the load transient response is tested. The time between
the application of the load transient and the turn on of the P-channel MOSFET, the output capacitor must supply
all of the current required by the load. V
OUT
immediately shifts by an amount equal to ΔI
(LOAD)
x ESR, where ESR
is the effective series resistance of C
OUT
. ΔI
(LOAD)
begins to charge or discharge C
O
generating a feedback error
signal used by the regulator to return V
OUT
to its steady-state value. The results are most easily interpreted when
the device operates in PWM mode.
During this recovery time, V
OUT
can be monitored for settling time, overshoot or ringing that helps judge the
converter’s stability. Without any ringing, the loop has usually more than 45° of phase margin.
Because the damping factor of the circuitry is directly related to several resistive parameters (e.g., MOSFET
r
DS(on)
) that are temperature dependant, the loop stability analysis has to be done over the input voltage range,
load current range, and temperature range.
LAYOUT CONSIDERATIONS
As for all switching power supplies, the layout is an important step in the design. Proper function of the device
demands careful attention to PCB layout. Care must be taken in board layout to get the specified performance. If
the layout is not carefully done, the regulator could show poor line and/or load regulation, stability issues as well
as EMI problems. It is critical to provide a low inductance, impedance ground path. Therefore, use wide and
short traces for the main current paths. The input capacitor should be placed as close as possible to the IC pins
as well as the inductor and output capacitor.
Use a common Power GND node and a different node for the Signal GND to minimize the effects of ground
noise. Keep the common path to the GND PIN, which returns the small signal components and the high current
of the output capacitors as short as possible to avoid ground noise. The FB line should be connected to the
output capacitor and routed away from noisy components and traces (e.g. SW line).
Figure 55. Recommended PCB Layout for TPS6223X
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