Datasheet

COUT

CIN

AGND

PGND

VIN

VOUT

TPS62175, TPS62177

SLVSB35B –OCTOBER 2012–REVISED JANUARY 2014

www.ti.com

NOTE

DC Bias effect: High capacitance ceramic capacitors have a DC Bias effect, which has a

strong influence on the final effective capacitance. Therefore the right capacitor value has

to be chosen carefully. Package size and voltage rating in combination with dielectric

material are responsible for differences between the rated capacitor value and the

effective capacitance.

Layout Considerations

The input capacitor needs to be placed as close as possible to the IC pins (VIN, PGND). The inductor should be

placed close to the SW pin and connect directly to the output capacitor - minimizing the loop area between the

SW pin, inductor, output capacitor and PGND pin. Also, sensitive nodes like FB and VOS should be connected

with short wires, not nearby high dv/dt signals (e.g. SW). The feedback resistors, R

and R

, should be placed

close to the IC and connect directly to the AGND and FB pins.

A proper layout is critical for the operation of a switch mode power supply, even more at high switching

frequencies. Therefore the PCB layout of the TPS62175/7 demands careful attention to ensure operation and to

get the performance specified. A poor layout can lead to issues like poor regulation (both line and load), stability

and accuracy weaknesses, increased EMI radiation and noise sensitivity. See Figure 55 for the recommended

layout of the TPS62175, which is implemented on the EVM. Information can be found in the EVM Users Guide,

SLVU743. Alternatively, the EVM Gerber data are available for download here, SLVC453.

Figure 55. Layout Example

spacingspacing

The Exposed Thermal Pad must be soldered to AGND and on the circuit board for mechanical reliability and to

achieve appropriate power dissipation.

Product Folder Links: TPS62175 TPS62177